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Searched refs:__raw_readl (Results 1 – 25 of 201) sorted by relevance

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/arch/mips/sgi-ip22/
Dip22-nvram.c36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
64 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); in eeprom_cmd()
[all …]
/arch/arm/mach-pxa/
Dsmemc.c23 msc[0] = __raw_readl(MSC0); in pxa3xx_smemc_suspend()
24 msc[1] = __raw_readl(MSC1); in pxa3xx_smemc_suspend()
25 sxcnfg = __raw_readl(SXCNFG); in pxa3xx_smemc_suspend()
26 memclkcfg = __raw_readl(MEMCLKCFG); in pxa3xx_smemc_suspend()
27 csadrcfg[0] = __raw_readl(CSADRCFG0); in pxa3xx_smemc_suspend()
28 csadrcfg[1] = __raw_readl(CSADRCFG1); in pxa3xx_smemc_suspend()
29 csadrcfg[2] = __raw_readl(CSADRCFG2); in pxa3xx_smemc_suspend()
30 csadrcfg[3] = __raw_readl(CSADRCFG3); in pxa3xx_smemc_suspend()
78 unsigned long memclkcfg = __raw_readl(MEMCLKCFG); in pxa3xx_smemc_get_memclkdiv()
/arch/mips/loongson32/common/
Dirq.c28 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_ack()
37 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask()
46 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask_ack()
48 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_mask_ack()
57 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_unmask()
68 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
70 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
74 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
76 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
80 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
[all …]
/arch/sh/boards/mach-dreamcast/
Drtc.c39 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday()
40 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday()
42 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday()
43 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday()
71 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_settimeofday()
72 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_settimeofday()
74 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_settimeofday()
75 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_settimeofday()
/arch/mips/alchemy/common/
Dusb.c102 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
103 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl()
131 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ in __au1300_ohci_control()
139 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ohci_control()
148 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ohci_control()
153 r = __raw_readl(base + USB_DWC_CTRL3); in __au1300_ohci_control()
168 r = __raw_readl(base + USB_DWC_CTRL3); in __au1300_ehci_control()
173 r = __raw_readl(base + USB_DWC_CTRL1); in __au1300_ehci_control()
180 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ehci_control()
185 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ehci_control()
[all …]
/arch/arm/mach-s3c/
Dpm-gpio.c29 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_1bit_save()
30 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_1bit_save()
36 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
37 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_1bit_resume()
66 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_2bit_save()
67 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_2bit_save()
68 chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP); in samsung_gpio_pm_2bit_save()
123 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_2bit_resume()
124 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_2bit_resume()
194 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_4bit_save()
[all …]
/arch/mips/pci/
Dops-tx4927.c69 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in mkaddr()
80 while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB) in check_abort()
82 if (__raw_readl(&pcicptr->pcistatus) in check_abort()
84 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in check_abort()
110 return __raw_readl(&pcicptr->g2pcfgdata); in icd_readl()
230 __raw_readl(&pcicptr->pciid) >> 16, in tx4927_pcic_setup()
231 __raw_readl(&pcicptr->pciid) & 0xffff, in tx4927_pcic_setup()
232 __raw_readl(&pcicptr->pciccrev) & 0xff, in tx4927_pcic_setup()
239 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
307 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
[all …]
Dpci-ar724x.c60 reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET); in ar724x_pci_check_link()
86 data = __raw_readl(base + (where & ~3)); in ar724x_pci_local_write()
108 __raw_readl(base + (where & ~3)); in ar724x_pci_local_write()
128 data = __raw_readl(base + (where & ~3)); in ar724x_pci_read()
197 data = __raw_readl(base + (where & ~3)); in ar724x_pci_write()
219 __raw_readl(base + (where & ~3)); in ar724x_pci_write()
238 pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & in ar724x_pci_irq_handler()
239 __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_handler()
261 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_unmask()
265 __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_unmask()
[all …]
Dpci-alchemy.c114 r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; in config_access()
157 *data = __raw_readl(ctx->pci_cfg_vm->addr + offset); in config_access()
164 status = __raw_readl(ctx->regs + PCI_REG_STATCMD); in config_access()
313 ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); in alchemy_pci_suspend()
314 ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; in alchemy_pci_suspend()
315 ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); in alchemy_pci_suspend()
316 ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); in alchemy_pci_suspend()
317 ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); in alchemy_pci_suspend()
318 ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); in alchemy_pci_suspend()
319 ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); in alchemy_pci_suspend()
[all …]
Dpci-ar71xx.c113 pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3; in ar71xx_pci_check_error()
118 addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR); in ar71xx_pci_check_error()
127 ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1; in ar71xx_pci_check_error()
132 addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR); in ar71xx_pci_check_error()
193 data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA); in ar71xx_pci_read_config()
234 pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & in ar71xx_pci_irq_handler()
235 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_handler()
263 t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_unmask()
267 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_unmask()
280 t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_mask()
[all …]
/arch/mips/ralink/
Dmt7621.c71 if (__raw_readl(dm) != __raw_readl(dm + size)) in mt7621_addr_wraparound_test()
74 return __raw_readl(dm) == __raw_readl(dm + size); in mt7621_addr_wraparound_test()
94 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0); in mt7621_get_soc_name0()
99 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME1); in mt7621_get_soc_name1()
121 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_REV); in mt7621_get_soc_rev()
Dmt7620.c98 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME0); in mt7620_get_soc_name0()
103 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME1); in mt7620_get_soc_name1()
126 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_REV); in mt7620_get_rev()
136 return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_EFUSE_CFG); in mt7620_get_efuse()
231 cfg0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG0); in prom_soc_init()
247 pmu0 = __raw_readl(MT7620_SYSC_BASE + PMU0_CFG); in prom_soc_init()
248 pmu1 = __raw_readl(MT7620_SYSC_BASE + PMU1_CFG); in prom_soc_init()
/arch/sh/kernel/cpu/sh4a/
Dubc.c50 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, in sh4a_ubc_enable_all()
59 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, in sh4a_ubc_disable_all()
69 if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE) in sh4a_ubc_active_mask()
77 return __raw_readl(UBC_CCMFR); in sh4a_ubc_triggered_mask()
82 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); in sh4a_ubc_clear_triggered_mask()
121 (void)__raw_readl(UBC_CRR(i)); in sh4a_ubc_init()
Dsmp-shx3.c34 x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */ in ipi_interrupt_handler()
51 __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu)); in shx3_smp_setup()
91 if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) in shx3_start_cpu()
94 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) in shx3_start_cpu()
103 return __raw_readl(0xff000048); /* CPIDR */ in shx3_smp_processor_id()
118 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) in shx3_update_boot_vector()
Dclock-sh7770.c21 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; in master_clk_init()
30 int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f); in module_clk_recalc()
40 int idx = (__raw_readl(FRQCR) & 0x000f); in bus_clk_recalc()
50 int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f); in cpu_clk_recalc()
Dclock-sh7780.c24 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; in master_clk_init()
33 int idx = (__raw_readl(FRQCR) & 0x0003); in module_clk_recalc()
43 int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007); in bus_clk_recalc()
53 int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001); in cpu_clk_recalc()
76 int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007); in shyway_clk_recalc()
Dperf_event.c229 return __raw_readl(PPC_PMCTR(idx)); in sh4a_pmu_read()
236 tmp = __raw_readl(PPC_CCBR(idx)); in sh4a_pmu_disable()
245 tmp = __raw_readl(PPC_PMCAT); in sh4a_pmu_enable()
250 tmp = __raw_readl(PPC_CCBR(idx)); in sh4a_pmu_enable()
254 __raw_writel(__raw_readl(PPC_CCBR(idx)) | CCBR_DUC, PPC_CCBR(idx)); in sh4a_pmu_enable()
262 __raw_writel(__raw_readl(PPC_CCBR(i)) & ~CCBR_DUC, PPC_CCBR(i)); in sh4a_pmu_disable_all()
270 __raw_writel(__raw_readl(PPC_CCBR(i)) | CCBR_DUC, PPC_CCBR(i)); in sh4a_pmu_enable_all()
/arch/arm/mach-davinci/
Dpm.c50 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
57 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
63 val = __raw_readl(pm_config.deepsleep_reg); in davinci_pm_suspend()
74 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
79 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
87 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
95 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
/arch/mips/ath79/
Dclock.c105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
131 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); in ar724x_clocks_init()
165 clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG); in ar933x_clocks_init()
178 cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG); in ar933x_clocks_init()
253 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); in ar934x_clocks_init()
257 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); in ar934x_clocks_init()
265 pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG); in ar934x_clocks_init()
280 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); in ar934x_clocks_init()
284 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); in ar934x_clocks_init()
292 pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG); in ar934x_clocks_init()
[all …]
/arch/sh/kernel/cpu/sh3/
Dprobe.c30 data0 = __raw_readl(addr0); in cpu_probe()
32 data1 = __raw_readl(addr1); in cpu_probe()
36 data0 = __raw_readl(addr0); in cpu_probe()
39 data1 = __raw_readl(addr1); in cpu_probe()
42 data3 = __raw_readl(addr0); in cpu_probe()
/arch/arm/mach-s5pv210/
Dpm.c78 return __raw_readl(S5P_EINT_WAKEUP_MASK); in s5pv210_read_eint_wakeup_mask()
117 tmp = __raw_readl(S5P_SLEEP_CFG); in s5pv210_pm_prepare()
122 tmp = __raw_readl(S5P_PWR_CFG); in s5pv210_pm_prepare()
128 tmp = __raw_readl(S5P_OTHERS); in s5pv210_pm_prepare()
167 __raw_readl(S5P_WAKEUP_STAT)); in s5pv210_suspend_enter()
/arch/arm/mach-lpc32xx/
Dcommon.c27 devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2)); in lpc32xx_get_uid()
43 savedval1 = __raw_readl(iramptr1); in lpc32xx_return_iram()
44 savedval2 = __raw_readl(iramptr2); in lpc32xx_return_iram()
48 if (__raw_readl(iramptr1) == savedval2 + 1) in lpc32xx_return_iram()
67 u32 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); in lpc32xx_set_phy_interface_mode()
/arch/sh/drivers/pci/
Dpci-sh7751.c24 word = __raw_readl(SH7751_BCR1); in __area_sdram_check()
94 reg = __raw_readl(SH7751_BCR1); in sh7751_pci_init()
156 word = __raw_readl(SH7751_WCR1); in sh7751_pci_init()
158 word = __raw_readl(SH7751_WCR2); in sh7751_pci_init()
160 word = __raw_readl(SH7751_WCR3); in sh7751_pci_init()
162 word = __raw_readl(SH7751_MCR); in sh7751_pci_init()
/arch/arm/boot/compressed/
Dmisc-ep93xx.h8 static inline unsigned int __raw_readl(unsigned int ptr) in __raw_readl() function
37 v = __raw_readl(PHYS_ETH_SELF_CTL); in ep93xx_ethernet_reset()
41 while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET) in ep93xx_ethernet_reset()
/arch/sparc/lib/
DPeeCeeI.c152 *pi++ = __raw_readl(addr); in insl()
162 l = __raw_readl(addr); in insl()
166 l2 = __raw_readl(addr); in insl()
177 l = __raw_readl(addr); in insl()
183 l2 = __raw_readl(addr); in insl()
194 l = __raw_readl(addr); in insl()
198 l2 = __raw_readl(addr); in insl()

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