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Searched refs:cntr (Results 1 – 6 of 6) sorted by relevance

/arch/mips/sibyte/common/
Dbus_watcher.c155 unsigned long cntr; in sibyte_bw_int() local
176 stats->l2_err = cntr = csr_in32(IOADDR(A_BUS_L2_ERRORS)); in sibyte_bw_int()
177 stats->l2_cor_d += G_SCD_L2ECC_CORR_D(cntr); in sibyte_bw_int()
178 stats->l2_bad_d += G_SCD_L2ECC_BAD_D(cntr); in sibyte_bw_int()
179 stats->l2_cor_t += G_SCD_L2ECC_CORR_T(cntr); in sibyte_bw_int()
180 stats->l2_bad_t += G_SCD_L2ECC_BAD_T(cntr); in sibyte_bw_int()
183 stats->memio_err = cntr = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); in sibyte_bw_int()
184 stats->mem_cor_d += G_SCD_MEM_ECC_CORR(cntr); in sibyte_bw_int()
185 stats->mem_bad_d += G_SCD_MEM_ECC_BAD(cntr); in sibyte_bw_int()
186 stats->bus_error += G_SCD_MEM_BUSERR(cntr); in sibyte_bw_int()
/arch/x86/events/intel/
Dp4.c27 signed char cntr[2][P4_CNTR_LIMIT]; /* counter index (offset), -1 on absence */ member
84 .cntr = { {4, 5, -1}, {6, 7, -1} },
91 .cntr = { {0, -1, -1}, {2, -1, -1} },
100 .cntr = { {0, -1, -1}, {2, -1, -1} },
108 .cntr = { {8, 9, -1}, {10, 11, -1} },
116 .cntr = { {8, 9, -1}, {10, 11, -1} },
123 .cntr = { {8, 9, -1}, {10, 11, -1} },
130 .cntr = { {8, 9, -1}, {10, 11, -1} },
140 .cntr = { {0, -1, -1}, {2, -1, -1} },
149 .cntr = { {0, -1, -1}, {2, -1, -1} },
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Dcore.c2391 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) in intel_tfa_commit_scheduling() argument
2396 if (cntr == 3) in intel_tfa_commit_scheduling()
3420 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) in intel_commit_scheduling() argument
3441 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; in intel_commit_scheduling()
3443 xl->state[cntr] = INTEL_EXCL_SHARED; in intel_commit_scheduling()
/arch/x86/events/amd/
Diommu.c158 u32 shift, bank, cntr; in get_next_avail_iommu_bnk_cntr() local
165 for (cntr = 0; cntr < max_cntrs; cntr++) { in get_next_avail_iommu_bnk_cntr()
166 shift = bank + (bank*3) + cntr; in get_next_avail_iommu_bnk_cntr()
172 event->hw.iommu_cntr = cntr; in get_next_avail_iommu_bnk_cntr()
185 u8 bank, u8 cntr) in clear_avail_iommu_bnk_cntr() argument
194 if ((bank > max_banks) || (cntr > max_cntrs)) in clear_avail_iommu_bnk_cntr()
197 shift = bank + cntr + (bank*3); in clear_avail_iommu_bnk_cntr()
242 u8 cntr = hwc->iommu_cntr; in perf_iommu_enable_event() local
246 amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_COUNTER_SRC_REG, &reg); in perf_iommu_enable_event()
252 amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DEVID_MATCH_REG, &reg); in perf_iommu_enable_event()
[all …]
/arch/x86/events/
Dperf_event.h785 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr);
/arch/mips/include/asm/octeon/
Dcvmx-mio-defs.h2783 uint64_t cntr:64; member
2785 uint64_t cntr:64;