| /arch/arm/mach-sa1100/ |
| D | clock.c | 23 static int clk_gpio27_enable(struct clk_hw *hw) in clk_gpio27_enable() argument
39 static void clk_gpio27_disable(struct clk_hw *hw) in clk_gpio27_disable() argument
71 static unsigned long clk_mpll_recalc_rate(struct clk_hw *hw, in clk_mpll_recalc_rate() argument
95 struct clk_hw *hw; in sa11xx_clk_init() local
98 hw = clk_hw_register_fixed_rate(NULL, "clk32768", NULL, 0, 32768); in sa11xx_clk_init()
99 if (IS_ERR(hw)) in sa11xx_clk_init()
100 return PTR_ERR(hw); in sa11xx_clk_init()
102 clk_hw_register_clkdev(hw, NULL, "sa1100-rtc"); in sa11xx_clk_init()
104 hw = clk_hw_register_fixed_rate(NULL, "clk3686400", NULL, 0, 3686400); in sa11xx_clk_init()
105 if (IS_ERR(hw)) in sa11xx_clk_init()
[all …]
|
| /arch/arm/boot/dts/nvidia/ |
| D | tegra124-peripherals-opp.dtsi | 10 opp-supported-hw = <0x0003>;
16 opp-supported-hw = <0x0008>;
22 opp-supported-hw = <0x0010>;
28 opp-supported-hw = <0x0004>;
34 opp-supported-hw = <0x0003>;
40 opp-supported-hw = <0x0008>;
46 opp-supported-hw = <0x0010>;
52 opp-supported-hw = <0x0004>;
58 opp-supported-hw = <0x0003>;
64 opp-supported-hw = <0x0008>;
[all …]
|
| D | tegra30-peripherals-opp.dtsi | 60 opp-supported-hw = <0x0006>;
67 opp-supported-hw = <0x0001>;
74 opp-supported-hw = <0x0008>;
81 opp-supported-hw = <0x0006>;
88 opp-supported-hw = <0x0001>;
95 opp-supported-hw = <0x0008>;
102 opp-supported-hw = <0x0006>;
109 opp-supported-hw = <0x0001>;
116 opp-supported-hw = <0x0008>;
123 opp-supported-hw = <0x0006>;
[all …]
|
| D | tegra20-peripherals-opp.dtsi | 50 opp-supported-hw = <0x000F>;
57 opp-supported-hw = <0x000F>;
64 opp-supported-hw = <0x000F>;
71 opp-supported-hw = <0x000F>;
78 opp-supported-hw = <0x000F>;
85 opp-supported-hw = <0x000F>;
92 opp-supported-hw = <0x000F>;
99 opp-supported-hw = <0x000F>;
106 opp-supported-hw = <0x000F>;
113 opp-supported-hw = <0x000F>;
[all …]
|
| D | tegra20-cpu-opp.dtsi | 10 opp-supported-hw = <0x0F 0x0003>;
17 opp-supported-hw = <0x0F 0x0004>;
24 opp-supported-hw = <0x0F 0x0003>;
30 opp-supported-hw = <0x0F 0x0004>;
36 opp-supported-hw = <0x0C 0x0003>;
42 opp-supported-hw = <0x03 0x0006>, <0x04 0x0004>,
49 opp-supported-hw = <0x03 0x0001>;
55 opp-supported-hw = <0x08 0x0003>;
61 opp-supported-hw = <0x04 0x0006>, <0x08 0x0004>;
67 opp-supported-hw = <0x04 0x0001>;
[all …]
|
| D | tegra30-cpu-opp.dtsi | 10 opp-supported-hw = <0x1F 0x31FE>;
16 opp-supported-hw = <0x1F 0x0C01>;
22 opp-supported-hw = <0x1F 0x0200>;
28 opp-supported-hw = <0x1F 0x31FE>;
34 opp-supported-hw = <0x1F 0x0C01>;
40 opp-supported-hw = <0x1F 0x0200>;
46 opp-supported-hw = <0x1F 0x31FE>;
53 opp-supported-hw = <0x1F 0x0C01>;
60 opp-supported-hw = <0x1F 0x0200>;
67 opp-supported-hw = <0x1F 0x0C00>;
[all …]
|
| /arch/arm/mach-omap1/ |
| D | clock_data.c | 77 .hw.init = CLK_HW_INIT_NO_PARENT("ck_ref", &omap1_clk_rate_ops, 0),
82 .hw.init = CLK_HW_INIT("ck_dpll1", "ck_ref", &omap1_clk_rate_ops,
96 .hw.init = CLK_HW_INIT("ck_dpll1out", "ck_dpll1", &omap1_clk_gate_ops, 0),
106 .hw.init = CLK_HW_INIT("ck_sossi", "ck_dpll1out", &omap1_clk_full_ops, 0),
117 .hw.init = CLK_HW_INIT("arm_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
126 .hw.init = CLK_HW_INIT("armper_ck", "ck_dpll1", &omap1_clk_full_ops,
145 .hw.init = CLK_HW_INIT("ick", "ck_dpll1", &omap1_clk_gate_ops, CLK_IS_CRITICAL),
153 .hw.init = CLK_HW_INIT("armxor_ck", "ck_ref", &omap1_clk_gate_ops,
165 .hw.init = CLK_HW_INIT("armtim_ck", "ck_ref", &omap1_clk_gate_ops,
177 .hw.init = CLK_HW_INIT("armwdt_ck", "ck_ref", &omap1_clk_full_ops, 0),
[all …]
|
| D | clock.c | 176 static int omap1_clk_is_enabled(struct clk_hw *hw) in omap1_clk_is_enabled() argument
178 struct omap1_clk *clk = to_omap1_clk(hw); in omap1_clk_is_enabled()
187 api_ck_was_enabled = omap1_clk_is_enabled(&api_ck_p->hw); in omap1_clk_is_enabled()
219 api_ck_was_enabled = omap1_clk_is_enabled(&api_ck_p->hw); in omap1_ckctl_recalc_dsp_domain()
503 static int omap1_clk_enable(struct clk_hw *hw) in omap1_clk_enable() argument
505 struct omap1_clk *clk = to_omap1_clk(hw), *parent = to_omap1_clk(clk_hw_get_parent(hw)); in omap1_clk_enable()
517 static void omap1_clk_disable(struct clk_hw *hw) in omap1_clk_disable() argument
519 struct omap1_clk *clk = to_omap1_clk(hw), *parent = to_omap1_clk(clk_hw_get_parent(hw)); in omap1_clk_disable()
536 clk_hw_get_name(&clk->hw)); in omap1_clk_enable_generic()
629 api_ck_was_enabled = omap1_clk_is_enabled(&api_ck_p->hw); in omap1_clk_enable_dsp_domain()
[all …]
|
| /arch/arm64/boot/dts/nvidia/ |
| D | tegra132-peripherals-opp.dtsi | 11 opp-supported-hw = <0x0003>;
17 opp-supported-hw = <0x0008>;
23 opp-supported-hw = <0x0010>;
29 opp-supported-hw = <0x0004>;
35 opp-supported-hw = <0x0003>;
41 opp-supported-hw = <0x0008>;
47 opp-supported-hw = <0x0010>;
53 opp-supported-hw = <0x0004>;
59 opp-supported-hw = <0x0003>;
65 opp-supported-hw = <0x0008>;
[all …]
|
| /arch/arm/mach-ep93xx/ |
| D | clock.c | 61 struct clk_hw hw; member
72 #define to_clk_psc(_hw) container_of(_hw, struct clk_psc, hw)
74 static int ep93xx_clk_is_enabled(struct clk_hw *hw) in ep93xx_clk_is_enabled() argument
76 struct clk_psc *psc = to_clk_psc(hw); in ep93xx_clk_is_enabled()
82 static int ep93xx_clk_enable(struct clk_hw *hw) in ep93xx_clk_enable() argument
84 struct clk_psc *psc = to_clk_psc(hw); in ep93xx_clk_enable()
102 static void ep93xx_clk_disable(struct clk_hw *hw) in ep93xx_clk_disable() argument
104 struct clk_psc *psc = to_clk_psc(hw); in ep93xx_clk_disable()
147 psc->hw.init = &init; in ep93xx_clk_register_gate()
150 clk = clk_register(NULL, &psc->hw); in ep93xx_clk_register_gate()
[all …]
|
| /arch/arm64/boot/dts/qcom/ |
| D | msm8996pro.dtsi | 14 * nibble of supported hw, so speed bin 0 becomes 0x10, speed bin 1
25 opp-supported-hw = <0x70>;
31 opp-supported-hw = <0x70>;
37 opp-supported-hw = <0x70>;
43 opp-supported-hw = <0x70>;
49 opp-supported-hw = <0x70>;
55 opp-supported-hw = <0x70>;
61 opp-supported-hw = <0x70>;
67 opp-supported-hw = <0x70>;
73 opp-supported-hw = <0x70>;
[all …]
|
| /arch/powerpc/perf/ |
| D | core-fsl-emb.c | 166 if (event->hw.state & PERF_HES_STOPPED) in fsl_emb_pmu_read()
175 prev = local64_read(&event->hw.prev_count); in fsl_emb_pmu_read()
177 val = read_pmc(event->hw.idx); in fsl_emb_pmu_read()
178 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); in fsl_emb_pmu_read()
183 local64_sub(delta, &event->hw.period_left); in fsl_emb_pmu_read()
287 if (event->hw.config & FSL_EMB_EVENT_RESTRICTED) in fsl_emb_pmu_add()
304 event->hw.idx = i; in fsl_emb_pmu_add()
309 if (event->hw.sample_period) { in fsl_emb_pmu_add()
310 s64 left = local64_read(&event->hw.period_left); in fsl_emb_pmu_add()
314 local64_set(&event->hw.prev_count, val); in fsl_emb_pmu_add()
[all …]
|
| D | core-book3s.c | 894 idx = cpuhw->event[i]->hw.idx; in any_pmc_overflown()
1161 if (event->hw.state & PERF_HES_STOPPED) in power_pmu_read()
1164 if (!event->hw.idx) in power_pmu_read()
1168 val = read_pmc(event->hw.idx); in power_pmu_read()
1169 local64_set(&event->hw.prev_count, val); in power_pmu_read()
1179 prev = local64_read(&event->hw.prev_count); in power_pmu_read()
1181 val = read_pmc(event->hw.idx); in power_pmu_read()
1185 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); in power_pmu_read()
1199 prev = local64_read(&event->hw.period_left); in power_pmu_read()
1203 } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); in power_pmu_read()
[all …]
|
| /arch/arm/mm/ |
| D | cache-l2x0-pmu.c | 119 struct hw_perf_event *hw = &event->hw; in l2x0_pmu_event_read() local
123 prev_count = local64_read(&hw->prev_count); in l2x0_pmu_event_read()
124 new_count = l2x0_pmu_counter_read(hw->idx); in l2x0_pmu_event_read()
125 } while (local64_xchg(&hw->prev_count, new_count) != prev_count); in l2x0_pmu_event_read()
135 struct hw_perf_event *hw = &event->hw; in l2x0_pmu_event_configure() local
147 local64_set(&hw->prev_count, 0); in l2x0_pmu_event_configure()
148 l2x0_pmu_counter_write(hw->idx, 0); in l2x0_pmu_event_configure()
188 struct hw_perf_event *hw = &event->hw; in l2x0_pmu_event_start() local
190 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) in l2x0_pmu_event_start()
194 WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE)); in l2x0_pmu_event_start()
[all …]
|
| /arch/mips/alchemy/common/ |
| D | clock.c | 118 static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw, in alchemy_clk_cpu_recalc() argument
180 struct clk_hw hw; member
184 #define to_auxpll_clk(x) container_of(x, struct alchemy_auxpll_clk, hw)
186 static unsigned long alchemy_clk_aux_recalc(struct clk_hw *hw, in alchemy_clk_aux_recalc() argument
189 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw); in alchemy_clk_aux_recalc()
194 static int alchemy_clk_aux_setr(struct clk_hw *hw, in alchemy_clk_aux_setr() argument
198 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw); in alchemy_clk_aux_setr()
214 static long alchemy_clk_aux_roundr(struct clk_hw *hw, in alchemy_clk_aux_roundr() argument
218 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw); in alchemy_clk_aux_roundr()
260 a->hw.init = &id; in alchemy_clk_setup_aux()
[all …]
|
| /arch/x86/kernel/ |
| D | hw_breakpoint.c | 234 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) in arch_check_bp_in_kernelspace() argument
239 va = hw->address; in arch_check_bp_in_kernelspace()
240 len = arch_bp_generic_len(hw->len); in arch_check_bp_in_kernelspace()
325 struct arch_hw_breakpoint *hw) in arch_build_bp_info() argument
342 hw->address = attr->bp_addr; in arch_build_bp_info()
343 hw->mask = 0; in arch_build_bp_info()
348 hw->type = X86_BREAKPOINT_WRITE; in arch_build_bp_info()
351 hw->type = X86_BREAKPOINT_RW; in arch_build_bp_info()
364 hw->type = X86_BREAKPOINT_EXECUTE; in arch_build_bp_info()
371 hw->len = X86_BREAKPOINT_LEN_X; in arch_build_bp_info()
[all …]
|
| /arch/sh/kernel/ |
| D | hw_breakpoint.c | 124 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) in arch_check_bp_in_kernelspace() argument
129 va = hw->address; in arch_check_bp_in_kernelspace()
130 len = get_hbp_len(hw->len); in arch_check_bp_in_kernelspace()
176 struct arch_hw_breakpoint *hw) in arch_build_bp_info() argument
178 hw->address = attr->bp_addr; in arch_build_bp_info()
183 hw->len = SH_BREAKPOINT_LEN_1; in arch_build_bp_info()
186 hw->len = SH_BREAKPOINT_LEN_2; in arch_build_bp_info()
189 hw->len = SH_BREAKPOINT_LEN_4; in arch_build_bp_info()
192 hw->len = SH_BREAKPOINT_LEN_8; in arch_build_bp_info()
201 hw->type = SH_BREAKPOINT_READ; in arch_build_bp_info()
[all …]
|
| D | perf_event.c | 103 struct hw_perf_event *hwc = &event->hw; in __hw_perf_event_init()
202 struct hw_perf_event *hwc = &event->hw; in sh_pmu_stop()
205 if (!(event->hw.state & PERF_HES_STOPPED)) { in sh_pmu_stop()
208 event->hw.state |= PERF_HES_STOPPED; in sh_pmu_stop()
211 if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) { in sh_pmu_stop()
212 sh_perf_event_update(event, &event->hw, idx); in sh_pmu_stop()
213 event->hw.state |= PERF_HES_UPTODATE; in sh_pmu_stop()
220 struct hw_perf_event *hwc = &event->hw; in sh_pmu_start()
227 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); in sh_pmu_start()
230 event->hw.state = 0; in sh_pmu_start()
[all …]
|
| /arch/arm/mach-omap2/ |
| D | clkt2xxx_virt_prcm_set.c | 73 static long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, in omap2_round_to_table_rate() argument
97 static int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, in omap2_select_table_rate() argument
231 struct clk_hw_omap *hw = NULL; in omap2xxx_clkt_vps_init() local
238 hw = kzalloc(sizeof(*hw), GFP_KERNEL); in omap2xxx_clkt_vps_init()
239 if (!hw) in omap2xxx_clkt_vps_init()
246 hw->hw.init = &init; in omap2xxx_clkt_vps_init()
248 clk = clk_register(NULL, &hw->hw); in omap2xxx_clkt_vps_init()
251 kfree(hw); in omap2xxx_clkt_vps_init()
|
| /arch/arm64/kernel/ |
| D | hw_breakpoint.c | 162 struct task_struct *tsk = bp->hw.target; in is_compat_bp()
335 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) in arch_check_bp_in_kernelspace() argument
340 va = hw->address; in arch_check_bp_in_kernelspace()
341 len = get_hbp_len(hw->ctrl.len); in arch_check_bp_in_kernelspace()
414 struct arch_hw_breakpoint *hw) in arch_build_bp_info() argument
419 hw->ctrl.type = ARM_BREAKPOINT_EXECUTE; in arch_build_bp_info()
422 hw->ctrl.type = ARM_BREAKPOINT_LOAD; in arch_build_bp_info()
425 hw->ctrl.type = ARM_BREAKPOINT_STORE; in arch_build_bp_info()
428 hw->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; in arch_build_bp_info()
437 hw->ctrl.len = ARM_BREAKPOINT_LEN_1; in arch_build_bp_info()
[all …]
|
| /arch/xtensa/kernel/ |
| D | hw_breakpoint.c | 37 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) in arch_check_bp_in_kernelspace() argument
42 va = hw->address; in arch_check_bp_in_kernelspace()
43 len = hw->len; in arch_check_bp_in_kernelspace()
53 struct arch_hw_breakpoint *hw) in hw_breakpoint_arch_parse() argument
58 hw->type = XTENSA_BREAKPOINT_EXECUTE; in hw_breakpoint_arch_parse()
61 hw->type = XTENSA_BREAKPOINT_LOAD; in hw_breakpoint_arch_parse()
64 hw->type = XTENSA_BREAKPOINT_STORE; in hw_breakpoint_arch_parse()
67 hw->type = XTENSA_BREAKPOINT_LOAD | XTENSA_BREAKPOINT_STORE; in hw_breakpoint_arch_parse()
74 hw->len = attr->bp_len; in hw_breakpoint_arch_parse()
75 if (hw->len < 1 || hw->len > 64 || !is_power_of_2(hw->len)) in hw_breakpoint_arch_parse()
[all …]
|
| /arch/powerpc/kernel/ |
| D | hw_breakpoint.c | 120 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) in arch_check_bp_in_kernelspace() argument
122 return is_kernel_addr(hw->address); in arch_check_bp_in_kernelspace()
156 static int hw_breakpoint_validate_len(struct arch_hw_breakpoint *hw) in hw_breakpoint_validate_len() argument
162 start_addr = ALIGN_DOWN(hw->address, HW_BREAKPOINT_SIZE); in hw_breakpoint_validate_len()
163 end_addr = ALIGN(hw->address + hw->len, HW_BREAKPOINT_SIZE); in hw_breakpoint_validate_len()
180 hw->hw_len = hw_len; in hw_breakpoint_validate_len()
189 struct arch_hw_breakpoint *hw) in hw_breakpoint_arch_parse() argument
196 hw->type = HW_BRK_TYPE_TRANSLATE; in hw_breakpoint_arch_parse()
198 hw->type |= HW_BRK_TYPE_READ; in hw_breakpoint_arch_parse()
200 hw->type |= HW_BRK_TYPE_WRITE; in hw_breakpoint_arch_parse()
[all …]
|
| /arch/arm/kernel/ |
| D | hw_breakpoint.c | 451 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) in arch_check_bp_in_kernelspace() argument
456 va = hw->address; in arch_check_bp_in_kernelspace()
457 len = get_hbp_len(hw->ctrl.len); in arch_check_bp_in_kernelspace()
514 struct arch_hw_breakpoint *hw) in arch_build_bp_info() argument
519 hw->ctrl.type = ARM_BREAKPOINT_EXECUTE; in arch_build_bp_info()
522 hw->ctrl.type = ARM_BREAKPOINT_LOAD; in arch_build_bp_info()
525 hw->ctrl.type = ARM_BREAKPOINT_STORE; in arch_build_bp_info()
528 hw->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; in arch_build_bp_info()
537 hw->ctrl.len = ARM_BREAKPOINT_LEN_1; in arch_build_bp_info()
540 hw->ctrl.len = ARM_BREAKPOINT_LEN_2; in arch_build_bp_info()
[all …]
|
| D | bios32.c | 426 static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, in pcibios_init_hw() argument
433 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) { in pcibios_init_hw()
443 sys->swizzle = hw->swizzle; in pcibios_init_hw()
444 sys->map_irq = hw->map_irq; in pcibios_init_hw()
447 if (hw->private_data) in pcibios_init_hw()
448 sys->private_data = hw->private_data[nr]; in pcibios_init_hw()
450 ret = hw->setup(nr, sys); in pcibios_init_hw()
463 if (hw->scan) in pcibios_init_hw()
464 ret = hw->scan(nr, bridge); in pcibios_init_hw()
471 bridge->ops = hw->ops; in pcibios_init_hw()
[all …]
|
| /arch/loongarch/kernel/ |
| D | hw_breakpoint.c | 189 if (bp->hw.target) in hw_breakpoint_control()
190 regs = task_pt_regs(bp->hw.target); in hw_breakpoint_control()
224 if (bp->hw.target && test_tsk_thread_flag(bp->hw.target, TIF_LOAD_WATCH)) in hw_breakpoint_control()
240 if (bp->hw.target) in hw_breakpoint_control()
286 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) in arch_check_bp_in_kernelspace() argument
291 va = hw->address; in arch_check_bp_in_kernelspace()
292 len = get_hbp_len(hw->ctrl.len); in arch_check_bp_in_kernelspace()
349 struct arch_hw_breakpoint *hw) in arch_build_bp_info() argument
354 hw->ctrl.type = LOONGARCH_BREAKPOINT_EXECUTE; in arch_build_bp_info()
357 hw->ctrl.type = LOONGARCH_BREAKPOINT_LOAD; in arch_build_bp_info()
[all …]
|