| /arch/powerpc/net/ |
| D | bpf_jit_comp32.c | 305 s32 imm = insn[i].imm; in bpf_jit_build_body() local
315 insn[i - 1].dst_reg == insn[i].dst_reg && insn[i - 1].imm != 1) { in bpf_jit_build_body()
367 imm = -imm; in bpf_jit_build_body()
370 if (!imm) { in bpf_jit_build_body()
372 } else if (IMM_HA(imm) & 0xffff) { in bpf_jit_build_body()
373 EMIT(PPC_RAW_ADDIS(dst_reg, src2_reg, IMM_HA(imm))); in bpf_jit_build_body()
376 if (IMM_L(imm)) in bpf_jit_build_body()
377 EMIT(PPC_RAW_ADDI(dst_reg, src2_reg, IMM_L(imm))); in bpf_jit_build_body()
380 imm = -imm; in bpf_jit_build_body()
383 if (!imm) { in bpf_jit_build_body()
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| D | bpf_jit_comp64.c | 384 s32 imm = insn[i].imm; in bpf_jit_build_body() local
428 if (!imm) { in bpf_jit_build_body()
430 } else if (imm >= -32768 && imm < 32768) { in bpf_jit_build_body()
431 EMIT(PPC_RAW_ADDI(dst_reg, dst_reg, IMM_L(imm))); in bpf_jit_build_body()
433 PPC_LI32(tmp1_reg, imm); in bpf_jit_build_body()
439 if (!imm) { in bpf_jit_build_body()
441 } else if (imm > -32768 && imm <= 32768) { in bpf_jit_build_body()
442 EMIT(PPC_RAW_ADDI(dst_reg, dst_reg, IMM_L(-imm))); in bpf_jit_build_body()
444 PPC_LI32(tmp1_reg, imm); in bpf_jit_build_body()
457 if (imm >= -32768 && imm < 32768) in bpf_jit_build_body()
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| /arch/arm/net/ |
| D | bpf_jit_32.h | 164 #define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm)) argument
170 #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm) argument
171 #define ARM_ADDS_I(rd, rn, imm) _AL3_I(ARM_INST_ADDS, rd, rn, imm) argument
173 #define ARM_ADC_I(rd, rn, imm) _AL3_I(ARM_INST_ADC, rd, rn, imm) argument
177 #define ARM_AND_I(rd, rn, imm) _AL3_I(ARM_INST_AND, rd, rn, imm) argument
180 #define ARM_BIC_I(rd, rn, imm) _AL3_I(ARM_INST_BIC, rd, rn, imm) argument
187 #define ARM_CMP_I(rn, imm) _AL3_I(ARM_INST_CMP, 0, rn, imm) argument
190 #define ARM_EOR_I(rd, rn, imm) _AL3_I(ARM_INST_EOR, rd, rn, imm) argument
195 #define ARM_LDR_R_SI(rt, rn, rm, type, imm) \ argument
198 | (imm) << 7 | (type) << 5 | (rm))
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| /arch/loongarch/kernel/ |
| D | inst.c | 17 unsigned int imm = insn.reg1i20_format.immediate; in simu_pc() local
26 regs->regs[rd] = pc + sign_extend64(imm << 2, 21); in simu_pc()
29 regs->regs[rd] = pc + sign_extend64(imm << 12, 31); in simu_pc()
32 regs->regs[rd] = pc + sign_extend64(imm << 18, 37); in simu_pc()
35 regs->regs[rd] = pc + sign_extend64(imm << 12, 31); in simu_pc()
48 unsigned int imm, imm_l, imm_h, rd, rj; in simu_branch() local
86 imm = insn.reg2i16_format.immediate; in simu_branch()
92 regs->csr_era = pc + sign_extend64(imm << 2, 17); in simu_branch()
98 regs->csr_era = pc + sign_extend64(imm << 2, 17); in simu_branch()
104 regs->csr_era = pc + sign_extend64(imm << 2, 17); in simu_branch()
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| /arch/mips/net/ |
| D | bpf_jit_comp.c | 192 void emit_mov_i(struct jit_context *ctx, u8 dst, s32 imm) in emit_mov_i() argument
194 if (imm >= -0x8000 && imm <= 0x7fff) { in emit_mov_i()
195 emit(ctx, addiu, dst, MIPS_R_ZERO, imm); in emit_mov_i()
197 emit(ctx, lui, dst, (s16)((u32)imm >> 16)); in emit_mov_i()
198 emit(ctx, ori, dst, dst, (u16)(imm & 0xffff)); in emit_mov_i()
211 bool valid_alu_i(u8 op, s32 imm) in valid_alu_i() argument
224 return imm >= -0x8000 && imm <= 0x7fff; in valid_alu_i()
229 return imm >= -0x7fff && imm <= 0x8000; in valid_alu_i()
234 return imm >= 0 && imm <= 0xffff; in valid_alu_i()
237 return imm == 0 || (imm > 0 && is_power_of_2(imm)); in valid_alu_i()
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| D | bpf_jit_comp32.c | 174 static void emit_mov_se_i64(struct jit_context *ctx, const u8 dst[], s32 imm) in emit_mov_se_i64() argument
176 emit_mov_i(ctx, lo(dst), imm); in emit_mov_se_i64()
177 if (imm < 0) in emit_mov_se_i64()
202 const u8 dst[], s32 imm, u8 op) in emit_alu_i64() argument
210 if (imm > S32_MIN && imm < 0) in emit_alu_i64()
214 imm = -imm; in emit_alu_i64()
218 imm = -imm; in emit_alu_i64()
223 emit_mov_i(ctx, src, imm); in emit_alu_i64()
231 if (imm < 0) in emit_alu_i64()
239 if (imm < 0) in emit_alu_i64()
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| D | bpf_jit_comp64.c | 158 static void emit_alu_i64(struct jit_context *ctx, u8 dst, s32 imm, u8 op) in emit_alu_i64() argument
163 emit(ctx, ori, dst, dst, (u16)imm); in emit_alu_i64()
167 emit(ctx, xori, dst, dst, (u16)imm); in emit_alu_i64()
175 emit(ctx, dsll_safe, dst, dst, imm); in emit_alu_i64()
179 emit(ctx, dsrl_safe, dst, dst, imm); in emit_alu_i64()
183 emit(ctx, dsra_safe, dst, dst, imm); in emit_alu_i64()
187 emit(ctx, daddiu, dst, dst, imm); in emit_alu_i64()
191 emit(ctx, daddiu, dst, dst, -imm); in emit_alu_i64()
195 emit_alu_i(ctx, dst, imm, op); in emit_alu_i64()
642 s32 imm = insn->imm; in build_insn() local
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| D | bpf_jit_comp.h | 160 void emit_mov_i(struct jit_context *ctx, u8 dst, s32 imm);
166 bool valid_alu_i(u8 op, s32 imm);
169 bool rewrite_alu_i(u8 op, s32 imm, u8 *alu, s32 *val);
172 void emit_alu_i(struct jit_context *ctx, u8 dst, s32 imm, u8 op);
187 bool valid_jmp_i(u8 op, s32 imm);
190 void setup_jmp_i(struct jit_context *ctx, s32 imm, u8 width,
201 void emit_jmp_i(struct jit_context *ctx, u8 dst, s32 imm, s32 off, u8 op);
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| /arch/arm/probes/kprobes/ |
| D | checkers-common.c | 34 int imm = insn & 0xff; in checker_stack_use_imm_0xx() local
35 asi->stack_space = imm; in checker_stack_use_imm_0xx()
47 int imm = insn & 0xff; in checker_stack_use_t32strd() local
48 asi->stack_space = imm << 2; in checker_stack_use_t32strd()
56 int imm = ((insn & 0xf00) >> 4) + (insn & 0xf); in checker_stack_use_imm_x0x() local
57 asi->stack_space = imm; in checker_stack_use_imm_x0x()
66 int imm = insn & 0xfff; in checker_stack_use_imm_xxx() local
67 asi->stack_space = imm; in checker_stack_use_imm_xxx()
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| /arch/riscv/net/ |
| D | bpf_jit.h | 266 u32 imm; in rv_j_insn() local
268 imm = (imm20_1 & 0x80000) | ((imm20_1 & 0x3ff) << 9) | in rv_j_insn()
271 return (imm << 12) | (rd << 7) | opcode; in rv_j_insn()
291 u32 imm; in rv_ci_insn() local
293 imm = ((imm6 & 0x20) << 7) | ((imm6 & 0x1f) << 2); in rv_ci_insn()
294 return (funct3 << 13) | (rd << 7) | op | imm; in rv_ci_insn()
329 u32 imm; in rv_cb_insn() local
331 imm = ((imm6 & 0x20) << 7) | ((imm6 & 0x1f) << 2); in rv_cb_insn()
332 return (funct3 << 13) | (funct2 << 10) | ((rd & 0x7) << 7) | op | imm; in rv_cb_insn()
608 u32 imm; in rvc_addi4spn() local
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| D | bpf_jit_comp32.c | 111 static void emit_imm(const s8 rd, s32 imm, struct rv_jit_context *ctx) in emit_imm() argument
113 u32 upper = (imm + (1 << 11)) >> 12; in emit_imm()
114 u32 lower = imm & 0xfff; in emit_imm()
124 static void emit_imm32(const s8 *rd, s32 imm, struct rv_jit_context *ctx) in emit_imm32() argument
127 emit_imm(lo(rd), imm, ctx); in emit_imm32()
130 if (imm >= 0) in emit_imm32()
243 static void emit_alu_i64(const s8 *dst, s32 imm, in emit_alu_i64() argument
251 emit_imm32(rd, imm, ctx); in emit_alu_i64()
254 if (is_12b_int(imm)) { in emit_alu_i64()
255 emit(rv_andi(lo(rd), lo(rd), imm), ctx); in emit_alu_i64()
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| /arch/arm64/net/ |
| D | bpf_jit.h | 73 #define A64_LS_IMM(Rt, Rn, imm, size, type) \ argument
74 aarch64_insn_gen_load_store_imm(Rt, Rn, imm, \
77 #define A64_STRBI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 8, STORE) argument
78 #define A64_LDRBI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 8, LOAD) argument
79 #define A64_LDRSBI(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 8, SIGNED_LOAD) argument
80 #define A64_STRHI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 16, STORE) argument
81 #define A64_LDRHI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 16, LOAD) argument
82 #define A64_LDRSHI(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 16, SIGNED_LOAD) argument
83 #define A64_STR32I(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 32, STORE) argument
84 #define A64_LDR32I(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 32, LOAD) argument
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| D | bpf_jit_comp.c | 35 #define check_imm(bits, imm) do { \ argument
36 if ((((imm) > 0) && ((imm) >> (bits))) || \
37 (((imm) < 0) && (~(imm) >> (bits)))) { \
39 i, imm, imm); \
43 #define check_imm19(imm) check_imm(19, imm) argument
44 #define check_imm26(imm) check_imm(26, imm) argument
218 static bool is_addsub_imm(u32 imm) in is_addsub_imm() argument
221 return !(imm & ~0xfff) || !(imm & ~0xfff000); in is_addsub_imm()
467 switch (insn->imm) { in emit_lse_atomic()
505 pr_err_once("unknown atomic op code %02x\n", insn->imm); in emit_lse_atomic()
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| /arch/riscv/kernel/ |
| D | alternative.c | 76 s32 imm; in riscv_alternative_fix_auipc_jalr() local
79 imm = riscv_insn_extract_utype_itype_imm(auipc_insn, jalr_insn); in riscv_alternative_fix_auipc_jalr()
80 imm -= patch_offset; in riscv_alternative_fix_auipc_jalr()
83 riscv_insn_insert_utype_itype_imm(&call[0], &call[1], imm); in riscv_alternative_fix_auipc_jalr()
91 s32 imm; in riscv_alternative_fix_jal() local
94 imm = riscv_insn_extract_jtype_imm(jal_insn); in riscv_alternative_fix_jal()
95 imm -= patch_offset; in riscv_alternative_fix_jal()
98 riscv_insn_insert_jtype_imm(&jal_insn, imm); in riscv_alternative_fix_jal()
134 s32 imm = riscv_insn_extract_jtype_imm(insn); in riscv_alternative_fix_offsets() local
137 if ((alt_ptr + i * sizeof(u32) + imm) >= alt_ptr && in riscv_alternative_fix_offsets()
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| /arch/loongarch/net/ |
| D | bpf_jit.h | 106 static inline void move_imm(struct jit_ctx *ctx, enum loongarch_gpr rd, long imm, bool is32) in move_imm() argument
111 if (imm == 0) { in move_imm()
117 if (is_signed_imm12(imm)) { in move_imm()
118 emit_insn(ctx, addiw, rd, LOONGARCH_GPR_ZERO, imm); in move_imm()
123 if (is_unsigned_imm12(imm)) { in move_imm()
124 emit_insn(ctx, ori, rd, LOONGARCH_GPR_ZERO, imm); in move_imm()
129 imm_63_52 = (imm >> 52) & 0xfff; in move_imm()
130 imm_51_0 = imm & 0xfffffffffffff; in move_imm()
137 imm_31_12 = (imm >> 12) & 0xfffff; in move_imm()
141 imm_11_0 = imm & 0xfff; in move_imm()
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| D | bpf_jit.c | 286 const s32 imm = insn->imm; in emit_atomic() local
293 switch (imm) { in emit_atomic()
463 const s32 imm = insn->imm; in build_insn() local
477 move_imm(ctx, dst, imm, is32); in build_insn()
490 if (is_signed_imm12(imm)) { in build_insn()
491 emit_insn(ctx, addid, dst, dst, imm); in build_insn()
493 move_imm(ctx, t1, imm, is32); in build_insn()
509 if (is_signed_imm12(-imm)) { in build_insn()
510 emit_insn(ctx, addid, dst, dst, -imm); in build_insn()
512 move_imm(ctx, t1, imm, is32); in build_insn()
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| /arch/arm64/lib/ |
| D | insn.c | 113 u32 insn, u64 imm) in aarch64_insn_encode_immediate() argument
124 immlo = (imm & ADR_IMM_LOMASK) << ADR_IMM_LOSHIFT; in aarch64_insn_encode_immediate()
125 imm >>= ADR_IMM_HILOSPLIT; in aarch64_insn_encode_immediate()
126 immhi = (imm & ADR_IMM_HIMASK) << ADR_IMM_HISHIFT; in aarch64_insn_encode_immediate()
127 imm = immlo | immhi; in aarch64_insn_encode_immediate()
141 insn |= (imm & mask) << shift; in aarch64_insn_encode_immediate()
412 unsigned int imm, in aarch64_insn_gen_load_store_imm() argument
425 if (imm & ~(BIT(12 + shift) - BIT(shift))) { in aarch64_insn_gen_load_store_imm()
426 pr_err("%s: invalid imm: %d\n", __func__, imm); in aarch64_insn_gen_load_store_imm()
430 imm >>= shift; in aarch64_insn_gen_load_store_imm()
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| /arch/s390/net/ |
| D | bpf_jit_comp.c | 186 #define EMIT4_IMM(op, b1, imm) \ argument
188 unsigned int __imm = (imm) & 0xffff; \
246 #define EMIT6_PCREL_RIEC(op1, op2, b1, imm, mask, target) \ argument
250 (rel & 0xffff), (op2) | ((imm) & 0xff) << 8); \
252 BUILD_BUG_ON(((unsigned long) (imm)) > 0xff); \
281 #define _EMIT6_IMM(op, imm) \ argument
283 unsigned int __imm = (imm); \
287 #define EMIT6_IMM(op, b1, imm) \ argument
289 _EMIT6_IMM((op) | reg_high(b1) << 16, imm); \
783 s32 imm = insn->imm; in bpf_jit_insn() local
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| /arch/parisc/net/ |
| D | bpf_jit_comp64.c | 135 static void emit_imm32(u8 rd, s32 imm, struct hppa_jit_context *ctx) in emit_imm32() argument
137 u32 lower = im11(imm); in emit_imm32()
140 if (OPTIMIZE_HPPA && relative_bits_ok(imm, 14)) { in emit_imm32()
141 emit(hppa_ldi(imm, rd), ctx); in emit_imm32()
144 if (OPTIMIZE_HPPA && lower == imm) { in emit_imm32()
148 emit(hppa_ldil(imm, rd), ctx); in emit_imm32()
160 static void emit_imm(u8 rd, s64 imm, u8 tmpreg, struct hppa_jit_context *ctx) in emit_imm() argument
165 emit_imm32(rd, imm, ctx); in emit_imm()
168 if (OPTIMIZE_HPPA && is_32b_int(imm)) in emit_imm()
172 upper32 = imm >> 32; in emit_imm()
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| D | bpf_jit_comp32.c | 141 static void emit_imm(const s8 rd, s32 imm, struct hppa_jit_context *ctx) in emit_imm() argument
143 u32 lower = im11(imm); in emit_imm()
146 if (OPTIMIZE_HPPA && relative_bits_ok(imm, 14)) { in emit_imm()
147 emit(hppa_ldi(imm, rd), ctx); in emit_imm()
150 emit(hppa_ldil(imm, rd), ctx); in emit_imm()
156 static void emit_imm32(const s8 *rd, s32 imm, struct hppa_jit_context *ctx) in emit_imm32() argument
160 emit_imm(lo(rd), imm, ctx); in emit_imm32()
164 if (imm >= 0) in emit_imm32()
421 static void emit_alu_i64(const s8 *dst, s32 imm, in emit_alu_i64() argument
435 emit_imm32(rd, imm, ctx); in emit_alu_i64()
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| /arch/sparc/net/ |
| D | bpf_jit_comp_64.c | 298 static void emit_alu_K(unsigned int opcode, unsigned int dst, unsigned int imm, in emit_alu_K() argument
301 bool small_immed = is_simm13(imm); in emit_alu_K()
306 emit(insn | IMMED | S13(imm), ctx); in emit_alu_K()
312 emit_set_const_sext(imm, tmp, ctx); in emit_alu_K()
317 static void emit_alu3_K(unsigned int opcode, unsigned int src, unsigned int imm, in emit_alu3_K() argument
320 bool small_immed = is_simm13(imm); in emit_alu3_K()
325 emit(insn | IMMED | S13(imm), ctx); in emit_alu3_K()
331 emit_set_const_sext(imm, tmp, ctx); in emit_alu3_K()
636 const u8 dst, s32 imm, struct jit_ctx *ctx) in emit_cbcondi() argument
640 emit(cb_opc | IMMED | WDISP10(off << 2) | RS1(dst) | S5(imm), ctx); in emit_cbcondi()
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| /arch/riscv/kernel/probes/ |
| D | simulate-insn.c | 44 u32 imm; in simulate_jal() local
51 imm = ((opcode >> 21) & 0x3ff) << 1; in simulate_jal()
52 imm |= ((opcode >> 20) & 0x1) << 11; in simulate_jal()
53 imm |= ((opcode >> 12) & 0xff) << 12; in simulate_jal()
54 imm |= ((opcode >> 31) & 0x1) << 20; in simulate_jal()
56 instruction_pointer_set(regs, addr + sign_extend32((imm), 20)); in simulate_jal()
70 u32 imm = (opcode >> 20) & 0xfff; in simulate_jalr() local
82 instruction_pointer_set(regs, (base_addr + sign_extend32((imm), 11))&~1); in simulate_jalr()
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| /arch/powerpc/lib/ |
| D | code-patching.c | 447 signed long imm; in branch_iform_target() local
449 imm = ppc_inst_val(ppc_inst_read(instr)) & 0x3FFFFFC; in branch_iform_target()
452 if (imm & 0x2000000) in branch_iform_target()
453 imm -= 0x4000000; in branch_iform_target()
456 imm += (unsigned long)instr; in branch_iform_target()
458 return (unsigned long)imm; in branch_iform_target()
463 signed long imm; in branch_bform_target() local
465 imm = ppc_inst_val(ppc_inst_read(instr)) & 0xFFFC; in branch_bform_target()
468 if (imm & 0x8000) in branch_bform_target()
469 imm -= 0x10000; in branch_bform_target()
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| /arch/riscv/include/asm/ |
| D | insn.h | 374 static inline void riscv_insn_insert_jtype_imm(u32 *insn, s32 imm) in riscv_insn_insert_jtype_imm() argument
378 *insn |= (RV_X(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OPOFF) | in riscv_insn_insert_jtype_imm()
379 (RV_X(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) | in riscv_insn_insert_jtype_imm()
380 (RV_X(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OPOFF) | in riscv_insn_insert_jtype_imm()
381 (RV_X(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF); in riscv_insn_insert_jtype_imm()
398 s32 imm; in riscv_insn_extract_utype_itype_imm() local
400 imm = RV_EXTRACT_UTYPE_IMM(utype_insn); in riscv_insn_extract_utype_itype_imm()
401 imm += RV_EXTRACT_ITYPE_IMM(itype_insn); in riscv_insn_extract_utype_itype_imm()
403 return imm; in riscv_insn_extract_utype_itype_imm()
421 static inline void riscv_insn_insert_utype_itype_imm(u32 *utype_insn, u32 *itype_insn, s32 imm) in riscv_insn_insert_utype_itype_imm() argument
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| /arch/loongarch/include/asm/ |
| D | inst.h | 485 u32 larch_insn_gen_break(int imm);
490 u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm);
491 u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
492 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
493 u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
507 int imm) \
510 insn->reg0i15_format.immediate = imm; \
535 enum loongarch_gpr rd, int imm) \
538 insn->reg1i20_format.immediate = imm; \
564 int imm) \
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