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Searched refs:operands (Results 1 – 16 of 16) sorted by relevance

/arch/powerpc/xmon/
Dppc.h60 unsigned char operands[8]; member
422 unsigned int operands; member
Dppc-dis.c102 for (opindex = opcode->operands; *opindex != 0; opindex++) in lookup_powerpc()
158 if (opcode->operands[0] != 0) in print_insn_powerpc()
171 for (opindex = opcode->operands; *opindex != 0; opindex++) in print_insn_powerpc()
/arch/m68k/fpsp040/
Ddo_func.S171 bra t_operr |take care of operands < -1
189 bne t_operr |take care of operands < 0
203 bra t_operr |take care of operands < 0
211 bne t_operr |take care of operands < 0
225 bra t_operr |take care of operands < 0
233 bne t_operr |take care of operands < 0
247 bra t_operr |take care of operands < 0
Dres_func.S605 | of the operands must be denormalized to enter this code.
650 | if(both operands are denorm)
664 | if(both operands are denorm)
824 | Check the signs of the operands. If they are unlike, the fpu
999 | Check the signs of the operands. If they are alike, the fpu
Ddecbin.S21 | and NaN operands are dispatched without entering this routine)
/arch/m68k/ifpsp060/
Dfplsp.doc101 addq.l &0x8,%sp # clear operands from stack
103 Again, the result is returned in fp0. Note that BOTH operands
/arch/s390/kernel/
Ddis.c135 static const struct s390_operand operands[] = { variable
446 operand = operands + *ops; in print_insn()
/arch/m68k/ifpsp060/src/
Dilsp.S84 # If the operands are signed, make them unsigned and save the #
545 # load temp registers with operands
603 # one or both of the operands is zero so the result is also zero.
671 # load temp registers with operands
Dfpsp.S2298 # have to make sure that for single or double source operands that the
2374 # set_tag_x() - determine optype of src/dst operands #
2376 # unnorm_fix() - change UNNORM operands to NORM or ZERO #
2948 # immediate operands but requires some extra work for fmovm dynamic
13951 # compute a result. Check if the regular operands would have taken #
14292 # compute a result. Check if the regular operands would have taken #
14608 # addsub_scaler2() - scale the operands so they won't take exc #
14958 # both operands are ZEROes
15018 # both operands are INFs. an OPERR will result if the INFs have
15031 # operands are INF and one of {ZERO, INF, DENORM, NORM}
[all …]
Dpfpsp.S2297 # have to make sure that for single or double source operands that the
2373 # set_tag_x() - determine optype of src/dst operands #
2375 # unnorm_fix() - change UNNORM operands to NORM or ZERO #
2947 # immediate operands but requires some extra work for fmovm dynamic
Dfplsp.S9349 # The input operands X and Y can be either normalized or #
/arch/arc/include/asm/
Dentry-arcv2.h168 ; ISA requires ADD.nz to have same dest and src reg operands
/arch/x86/math-emu/
DREADME113 (a) the operands have a higher precision than the current setting of the
119 operands were rounded to the current precision before the arithmetic
277 for operands close to pi/2. Measured results are (note that the
/arch/arc/
DKconfig363 dest operands with 2 possible source operands.
/arch/x86/lib/
Dx86-opcode-map.txt346 # NOTE: According to Intel SDM opcode map, vmovups and vmovupd has no operands
347 # but it actually has operands. And also, vmovss and vmovsd only accept 128bit.
/arch/x86/crypto/
Daesni-intel_asm.S1081 # XMM8 and TMP5 hold the values for the two operands
1289 # XMM8 and TMP5 hold the values for the two operands