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/arch/powerpc/lib/
Dtest-code-patching.c206 void *p, *q; in test_translate_branch() local
221 q = p + 4; in test_translate_branch()
222 translate_branch(&instr, q, p); in test_translate_branch()
223 ppc_inst_write(q, instr); in test_translate_branch()
224 check(instr_is_branch_to_addr(q, addr)); in test_translate_branch()
231 q = buf + 0x2000000; in test_translate_branch()
232 translate_branch(&instr, q, p); in test_translate_branch()
233 ppc_inst_write(q, instr); in test_translate_branch()
235 check(instr_is_branch_to_addr(q, addr)); in test_translate_branch()
236 check(ppc_inst_equal(ppc_inst_read(q), ppc_inst(0x4a000000))); in test_translate_branch()
[all …]
/arch/alpha/include/asm/
Dcore_wildfire.h227 #define WILDFIRE_QBB(q) ((~((long)(q)) & WILDFIRE_QBB_MASK) << 36) argument
230 #define WILDFIRE_QBB_IO(q) (WILDFIRE_BASE | WILDFIRE_QBB(q)) argument
231 #define WILDFIRE_QBB_HOSE(q,h) (WILDFIRE_QBB_IO(q) | WILDFIRE_HOSE(h)) argument
233 #define WILDFIRE_MEM(q,h) (WILDFIRE_QBB_HOSE(q,h) | 0x000000000UL) argument
234 #define WILDFIRE_CONF(q,h) (WILDFIRE_QBB_HOSE(q,h) | 0x1FE000000UL) argument
235 #define WILDFIRE_IO(q,h) (WILDFIRE_QBB_HOSE(q,h) | 0x1FF000000UL) argument
237 #define WILDFIRE_qsd(q) \ argument
238 ((wildfire_qsd *)(WILDFIRE_QBB_IO(q)|WILDFIRE_QSD_ENTITY_SLOW|(((1UL<<13)-1)<<23)))
243 #define WILDFIRE_qsa(q) \ argument
244 ((wildfire_qsa *)(WILDFIRE_QBB_IO(q)|WILDFIRE_QSA_ENTITY|(((1UL<<13)-1)<<23)))
[all …]
/arch/mips/math-emu/
Dsp_sqrt.c14 int ix, s, q, m, t, i; in ieee754sp_sqrt() local
74 q = 0; /* q = sqrt(x) */ in ieee754sp_sqrt()
82 q += r; in ieee754sp_sqrt()
92 q += 2; in ieee754sp_sqrt()
95 q += (q & 1); in ieee754sp_sqrt()
99 ix = (q >> 1) + 0x3f000000; in ieee754sp_sqrt()
/arch/mips/bmips/
Dsetup.c175 const struct bmips_quirk *q; in plat_mem_setup() local
195 for (q = bmips_quirk_list; q->quirk_fn; q++) { in plat_mem_setup()
197 q->compatible)) { in plat_mem_setup()
198 q->quirk_fn(); in plat_mem_setup()
/arch/x86/lib/
Dmsr.c46 m->q = val; in msr_read()
61 return wrmsrl_safe(msr, m->q); in msr_write()
78 m1.q |= BIT_64(bit); in __flip_bit()
80 m1.q &= ~BIT_64(bit); in __flip_bit()
82 if (m1.q == m.q) in __flip_bit()
Dmsr-smp.c52 int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) in rdmsrl_on_cpu() argument
61 *q = rv.reg.q; in rdmsrl_on_cpu()
83 int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) in wrmsrl_on_cpu() argument
91 rv.reg.q = q; in wrmsrl_on_cpu()
209 int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) in wrmsrl_safe_on_cpu() argument
217 rv.reg.q = q; in wrmsrl_safe_on_cpu()
225 int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) in rdmsrl_safe_on_cpu() argument
231 *q = (u64)high << 32 | low; in rdmsrl_safe_on_cpu()
/arch/x86/xen/
Dplatform-pci-unplug.c181 char *p, *q; in parse_xen_emul_unplug() local
184 for (p = arg; p; p = q) { in parse_xen_emul_unplug()
185 q = strchr(p, ','); in parse_xen_emul_unplug()
186 if (q) { in parse_xen_emul_unplug()
187 l = q - p; in parse_xen_emul_unplug()
188 q++; in parse_xen_emul_unplug()
/arch/sh/lib/
Ddiv64-generic.c14 uint64_t q = __xdiv64_32(*xp, y); in __div64_32() local
16 rem = *xp - q * y; in __div64_32()
17 *xp = q; in __div64_32()
/arch/arm/crypto/
Dsha2-ce-core.S40 vadd.u32 ta\ev, q\s0, k\ev
45 sha256su0.32 q\s0, q\s1
47 sha256su1.32 q\s0, q\s2, q\s3
Dsha1-ce-core.S38 vadd.u32 tb\ev, q\s0, \rc
49 sha1su0.32 q\s0, q\s1, q\s2
51 sha1su1.32 q\s0, q\s3
/arch/x86/math-emu/
Dfpu_trig.c22 unsigned long long st1, unsigned long long q, int n);
38 unsigned long long q; in trig_arg() local
56 q = significand(&tmp); in trig_arg()
57 if (q) { in trig_arg()
61 q, exponent(st0_ptr) - exponent(&CONST_PI2)); in trig_arg()
67 if ((even && !(q & 1)) || (!even && (q & 1))) { in trig_arg()
78 || (q > 1)) { in trig_arg()
82 significand(&tmp) = q + 1; in trig_arg()
98 q++; in trig_arg()
109 if (((q > 0) in trig_arg()
[all …]
/arch/arm64/crypto/
Dsm4-ce-gcm-core.S41 pmull r0.1q, m0.1d, m1.1d; \
42 pmull T1.1q, m0.1d, T0.1d; \
43 pmull2 T0.1q, m0.2d, T0.2d; \
44 pmull2 r1.1q, m0.2d, m1.2d; \
59 pmull r0.1q, m0.1d, m1.1d; \
60 pmull r2.1q, m2.1d, m3.1d; \
61 pmull r4.1q, m4.1d, m5.1d; \
62 pmull r6.1q, m6.1d, m7.1d; \
63 pmull T1.1q, m0.1d, T0.1d; \
64 pmull T3.1q, m2.1d, T2.1d; \
[all …]
Dpolyval-ce-core.S100 pmull2 v28.1q, X.2d, Y.2d
101 pmull v29.1q, X.1d, Y.1d
102 pmull v27.1q, v25.1d, v26.1d
121 pmull2 HI.1q, X.2d, Y.2d
122 pmull LO.1q, X.1d, Y.1d
123 pmull MI.1q, v25.1d, v26.1d
195 pmull TMP_V.1q, PL.1d, GSTAR.1d
203 pmull2 TMP_V.1q, TMP_V.2d, GSTAR.2d
228 pmull TMP_V.1q, PL.1d, GSTAR.1d
248 pmull2 TMP_V.1q, TMP_V.2d, GSTAR.2d
Dghash-ce-core.S64 pmull \rd\().1q, \rn\().1d, \rm\().1d
68 pmull2 \rd\().1q, \rn\().2d, \rm\().2d
201 pmull T2.1q, XL.1d, MASK.1d
209 pmull XL.1q, XL.1d, MASK.1d
269 pmull2 XH2.1q, SHASH.2d, IN1.2d // a1 * b1
270 pmull XL2.1q, SHASH.1d, IN1.1d // a0 * b0
271 pmull XM2.1q, SHASH2.1d, TT4.1d // (a1 + a0)(b1 + b0)
274 pmull2 XH3.1q, HH.2d, XL3.2d // a1 * b1
275 pmull XL3.1q, HH.1d, XL3.1d // a0 * b0
276 pmull2 XM3.1q, SHASH2.2d, TT3.2d // (a1 + a0)(b1 + b0)
[all …]
/arch/powerpc/platforms/powermac/
Dbootx_init.c47 const char *p, *q, *s; in bootx_printf() local
52 for (p = format; *p != 0; p = q) { in bootx_printf()
53 for (q = p; *q != 0 && *q != '\n' && *q != '%'; ++q) in bootx_printf()
55 if (q > p) in bootx_printf()
56 btext_drawtext(p, q - p); in bootx_printf()
57 if (*q == 0) in bootx_printf()
59 if (*q == '\n') { in bootx_printf()
60 ++q; in bootx_printf()
66 ++q; in bootx_printf()
67 if (*q == 0) in bootx_printf()
[all …]
/arch/x86/include/asm/
Dmsr.h316 int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
317 int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
322 int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
323 int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
337 static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) in rdmsrl_on_cpu() argument
339 rdmsrl(msr_no, *q); in rdmsrl_on_cpu()
342 static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) in wrmsrl_on_cpu() argument
344 wrmsrl(msr_no, q); in wrmsrl_on_cpu()
366 static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) in rdmsrl_safe_on_cpu() argument
368 return rdmsrl_safe(msr_no, q); in rdmsrl_safe_on_cpu()
[all …]
Ddiv64.h89 u64 q; in mul_u64_u64_div_u64() local
91 asm ("mulq %2; divq %3" : "=a" (q) in mul_u64_u64_div_u64()
95 return q; in mul_u64_u64_div_u64()
/arch/powerpc/sysdev/xive/
Dcommon.c103 static u32 xive_read_eq(struct xive_q *q, bool just_peek) in xive_read_eq() argument
107 if (!q->qpage) in xive_read_eq()
109 cur = be32_to_cpup(q->qpage + q->idx); in xive_read_eq()
112 if ((cur >> 31) == q->toggle) in xive_read_eq()
118 q->idx = (q->idx + 1) & q->msk; in xive_read_eq()
121 if (q->idx == 0) in xive_read_eq()
122 q->toggle ^= 1; in xive_read_eq()
158 struct xive_q *q; in xive_scan_interrupts() local
189 q = &xc->queue[prio]; in xive_scan_interrupts()
190 if (atomic_read(&q->pending_count)) { in xive_scan_interrupts()
[all …]
Dnative.c131 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, in xive_native_configure_queue() argument
148 q->msk = order ? ((1u << (order - 2)) - 1) : 0; in xive_native_configure_queue()
149 q->idx = 0; in xive_native_configure_queue()
150 q->toggle = 0; in xive_native_configure_queue()
161 q->eoi_phys = be64_to_cpu(qeoi_page_be); in xive_native_configure_queue()
168 q->esc_irq = be32_to_cpu(esc_irq_be); in xive_native_configure_queue()
188 q->qpage = qpage; in xive_native_configure_queue()
195 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) in __xive_native_disable_queue() argument
210 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) in xive_native_disable_queue() argument
212 __xive_native_disable_queue(vp_id, q, prio); in xive_native_disable_queue()
[all …]
Dspapr.c478 static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio, in xive_spapr_configure_queue() argument
496 q->msk = order ? ((1u << (order - 2)) - 1) : 0; in xive_spapr_configure_queue()
497 q->idx = 0; in xive_spapr_configure_queue()
498 q->toggle = 0; in xive_spapr_configure_queue()
509 q->eoi_phys = esn_page; in xive_spapr_configure_queue()
521 q->qpage = qpage; in xive_spapr_configure_queue()
533 struct xive_q *q = &xc->queue[prio]; in xive_spapr_setup_queue() local
541 q, prio, qpage, xive_queue_shift); in xive_spapr_setup_queue()
547 struct xive_q *q = &xc->queue[prio]; in xive_spapr_cleanup_queue() local
559 uv_unshare_page(PHYS_PFN(__pa(q->qpage)), 1 << alloc_order); in xive_spapr_cleanup_queue()
[all …]
/arch/sparc/math-emu/
Dmath_64.c164 u64 q[2]; member
457 case FMOVQ: rd->q[0] = rs2->q[0]; rd->q[1] = rs2->q[1]; break; in do_mathemu()
458 case FABSQ: rd->q[0] = rs2->q[0] & 0x7fffffffffffffffUL; rd->q[1] = rs2->q[1]; break; in do_mathemu()
459 case FNEGQ: rd->q[0] = rs2->q[0] ^ 0x8000000000000000UL; rd->q[1] = rs2->q[1]; break; in do_mathemu()
/arch/powerpc/kvm/
Dbook3s_xive.c141 struct xive_q *q; in xive_vm_scan_interrupts() local
161 q = &xc->queues[prio]; in xive_vm_scan_interrupts()
162 idx = q->idx; in xive_vm_scan_interrupts()
163 toggle = q->toggle; in xive_vm_scan_interrupts()
171 qpage = READ_ONCE(q->qpage); in xive_vm_scan_interrupts()
178 hirq = __xive_read_eq(qpage, q->msk, &idx, &toggle); in xive_vm_scan_interrupts()
198 q->idx = idx; in xive_vm_scan_interrupts()
199 q->toggle = toggle; in xive_vm_scan_interrupts()
219 if (atomic_read(&q->pending_count)) { in xive_vm_scan_interrupts()
220 int p = atomic_xchg(&q->pending_count, 0); in xive_vm_scan_interrupts()
[all …]
Dbook3s_xive_native.c47 struct xive_q *q = &xc->queues[prio]; in kvmppc_xive_native_cleanup_queue() local
49 xive_native_disable_queue(xc->vp_id, q, prio); in kvmppc_xive_native_cleanup_queue()
50 if (q->qpage) { in kvmppc_xive_native_cleanup_queue()
51 put_page(virt_to_page(q->qpage)); in kvmppc_xive_native_cleanup_queue()
52 q->qpage = NULL; in kvmppc_xive_native_cleanup_queue()
56 static int kvmppc_xive_native_configure_queue(u32 vp_id, struct xive_q *q, in kvmppc_xive_native_configure_queue() argument
61 __be32 *qpage_prev = q->qpage; in kvmppc_xive_native_configure_queue()
63 rc = xive_native_configure_queue(vp_id, q, prio, qpage, order, in kvmppc_xive_native_configure_queue()
572 struct xive_q *q; in kvmppc_xive_native_set_queue_config() local
600 q = &xc->queues[priority]; in kvmppc_xive_native_set_queue_config()
[all …]
/arch/powerpc/xmon/
Dnonstdio.c41 const char *p = ptr, *q; in xmon_write() local
51 while (paginating && (q = strchr(p, '\n'))) { in xmon_write()
52 rv += udbg_write(p, q - p + 1); in xmon_write()
53 p = q + 1; in xmon_write()
/arch/powerpc/crypto/
Dmd5-asm.S61 #define R_00_15(a, b, c, d, w0, w1, p, q, off, k0h, k0l, k1h, k1l) \ argument
82 rotrwi d,d,q; /* 2: a = a rotl x */ \
85 #define R_16_31(a, b, c, d, w0, w1, p, q, k0h, k0l, k1h, k1l) \ argument
102 rotrwi d,d,q; /* 2: a = a rotl x */ \
105 #define R_32_47(a, b, c, d, w0, w1, p, q, k0h, k0l, k1h, k1l) \ argument
119 rotrwi d,d,q; /* 2: a = a rotl x */ \
122 #define R_48_63(a, b, c, d, w0, w1, p, q, k0h, k0l, k1h, k1l) \ argument
137 rotrwi d,d,q; /* 2: a = a rotl x */ \

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