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/arch/x86/um/shared/sysdep/
Dptrace.h11 #define REGS_IP(r) ((r)[HOST_IP]) argument
12 #define REGS_SP(r) ((r)[HOST_SP]) argument
13 #define REGS_EFLAGS(r) ((r)[HOST_EFLAGS]) argument
14 #define REGS_AX(r) ((r)[HOST_AX]) argument
15 #define REGS_BX(r) ((r)[HOST_BX]) argument
16 #define REGS_CX(r) ((r)[HOST_CX]) argument
17 #define REGS_DX(r) ((r)[HOST_DX]) argument
18 #define REGS_SI(r) ((r)[HOST_SI]) argument
19 #define REGS_DI(r) ((r)[HOST_DI]) argument
20 #define REGS_BP(r) ((r)[HOST_BP]) argument
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Dptrace_64.h13 #define REGS_R8(r) ((r)[HOST_R8]) argument
14 #define REGS_R9(r) ((r)[HOST_R9]) argument
15 #define REGS_R10(r) ((r)[HOST_R10]) argument
16 #define REGS_R11(r) ((r)[HOST_R11]) argument
17 #define REGS_R12(r) ((r)[HOST_R12]) argument
18 #define REGS_R13(r) ((r)[HOST_R13]) argument
19 #define REGS_R14(r) ((r)[HOST_R14]) argument
20 #define REGS_R15(r) ((r)[HOST_R15]) argument
44 #define UPT_R8(r) REGS_R8((r)->gp) argument
45 #define UPT_R9(r) REGS_R9((r)->gp) argument
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Dptrace_32.h15 #define UPT_SYSCALL_ARG1(r) UPT_BX(r) argument
16 #define UPT_SYSCALL_ARG2(r) UPT_CX(r) argument
17 #define UPT_SYSCALL_ARG3(r) UPT_DX(r) argument
18 #define UPT_SYSCALL_ARG4(r) UPT_SI(r) argument
19 #define UPT_SYSCALL_ARG5(r) UPT_DI(r) argument
20 #define UPT_SYSCALL_ARG6(r) UPT_BP(r) argument
/arch/x86/um/asm/
Dptrace.h11 #define user_mode(r) UPT_IS_USER(&(r)->regs) argument
13 #define PT_REGS_AX(r) UPT_AX(&(r)->regs) argument
14 #define PT_REGS_BX(r) UPT_BX(&(r)->regs) argument
15 #define PT_REGS_CX(r) UPT_CX(&(r)->regs) argument
16 #define PT_REGS_DX(r) UPT_DX(&(r)->regs) argument
18 #define PT_REGS_SI(r) UPT_SI(&(r)->regs) argument
19 #define PT_REGS_DI(r) UPT_DI(&(r)->regs) argument
20 #define PT_REGS_BP(r) UPT_BP(&(r)->regs) argument
21 #define PT_REGS_EFLAGS(r) UPT_EFLAGS(&(r)->regs) argument
23 #define PT_REGS_CS(r) UPT_CS(&(r)->regs) argument
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/arch/powerpc/platforms/ps3/
Dmm.c217 static int __init ps3_mm_get_repository_highmem(struct mem_region *r) in ps3_mm_get_repository_highmem() argument
223 result = ps3_repository_read_highmem_info(0, &r->base, &r->size); in ps3_mm_get_repository_highmem()
228 if (!r->base || !r->size) { in ps3_mm_get_repository_highmem()
233 r->offset = r->base - map.rm.size; in ps3_mm_get_repository_highmem()
236 __func__, __LINE__, r->base, r->size); in ps3_mm_get_repository_highmem()
243 r->size = r->base = r->offset = 0; in ps3_mm_get_repository_highmem()
247 static int ps3_mm_set_repository_highmem(const struct mem_region *r) in ps3_mm_set_repository_highmem() argument
251 return r ? ps3_repository_write_highmem_info(0, r->base, r->size) : in ps3_mm_set_repository_highmem()
264 static int ps3_mm_region_create(struct mem_region *r, unsigned long size) in ps3_mm_region_create() argument
269 r->size = ALIGN_DOWN(size, 1 << PAGE_SHIFT_16M); in ps3_mm_region_create()
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/arch/x86/kernel/cpu/resctrl/
Dcore.c53 struct rdt_resource *r);
55 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r);
58 struct rdt_resource *r);
138 struct rdt_resource *r = &hw_res->r_resctrl; in cache_alloc_hsw_probe() local
151 r->default_ctrl = max_cbm; in cache_alloc_hsw_probe()
152 r->cache.cbm_len = 20; in cache_alloc_hsw_probe()
153 r->cache.shareable_bits = 0xc0000; in cache_alloc_hsw_probe()
154 r->cache.min_cbm_bits = 2; in cache_alloc_hsw_probe()
155 r->alloc_capable = true; in cache_alloc_hsw_probe()
160 bool is_mba_sc(struct rdt_resource *r) in is_mba_sc() argument
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Dctrlmondata.c30 static bool bw_validate(char *buf, unsigned long *data, struct rdt_resource *r) in bw_validate() argument
38 if (!r->membw.delay_linear && r->membw.arch_needs_linear) { in bw_validate()
49 if ((bw < r->membw.min_bw || bw > r->default_ctrl) && in bw_validate()
50 !is_mba_sc(r)) { in bw_validate()
52 r->membw.min_bw, r->default_ctrl); in bw_validate()
56 *data = roundup(bw, (unsigned long)r->membw.bw_gran); in bw_validate()
65 struct rdt_resource *r = s->res; in parse_bw() local
74 if (!bw_validate(data->buf, &bw_val, r)) in parse_bw()
77 if (is_mba_sc(r)) { in parse_bw()
96 static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r) in cbm_validate() argument
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Dinternal.h107 struct rdt_resource *r; member
333 static inline struct rdt_hw_domain *resctrl_to_arch_dom(struct rdt_domain *r) in resctrl_to_arch_dom() argument
335 return container_of(r, struct rdt_hw_domain, d_resctrl); in resctrl_to_arch_dom()
406 struct rdt_resource *r);
413 static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r) in resctrl_to_arch_res() argument
415 return container_of(r, struct rdt_hw_resource, r_resctrl); in resctrl_to_arch_res()
460 #define for_each_rdt_resource(r) \ argument
461 for (r = &rdt_resources_all[0].r_resctrl; \
462 r <= &rdt_resources_all[RDT_NUM_RESOURCES - 1].r_resctrl; \
463 r = resctrl_inc(r))
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Drdtgroup.c83 struct rdt_resource *r; in rdt_staged_configs_clear() local
88 for_each_alloc_capable_rdt_resource(r) { in rdt_staged_configs_clear()
89 list_for_each_entry(dom, &r->domains, list) in rdt_staged_configs_clear()
318 struct rdtgroup *r = info; in update_cpu_closid_rmid() local
320 if (r) { in update_cpu_closid_rmid()
321 this_cpu_write(pqr_state.default_closid, r->closid); in update_cpu_closid_rmid()
322 this_cpu_write(pqr_state.default_rmid, r->mon.rmid); in update_cpu_closid_rmid()
339 update_closid_rmid(const struct cpumask *cpu_mask, struct rdtgroup *r) in update_closid_rmid() argument
341 on_each_cpu_mask(cpu_mask, update_cpu_closid_rmid, r, 1); in update_closid_rmid()
387 static void cpumask_rdtgrp_clear(struct rdtgroup *r, struct cpumask *m) in cpumask_rdtgrp_clear() argument
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/arch/mips/alchemy/common/
Dusb.c100 unsigned long r, s; in __au1300_usb_phyctl() local
102 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
110 r |= USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS | in __au1300_usb_phyctl()
112 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
116 r &= ~(USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS | in __au1300_usb_phyctl()
118 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
125 unsigned long r; in __au1300_ohci_control() local
131 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ in __au1300_ohci_control()
132 r |= (id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN in __au1300_ohci_control()
134 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
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/arch/powerpc/include/asm/
Dpmac_feature.h367 #define MACIO_FCR32(macio, r) ((macio)->base + ((r) >> 2)) argument
368 #define MACIO_FCR8(macio, r) (((volatile u8 __iomem *)((macio)->base)) + (r)) argument
370 #define MACIO_IN32(r) (in_le32(MACIO_FCR32(macio,r))) argument
371 #define MACIO_OUT32(r,v) (out_le32(MACIO_FCR32(macio,r), (v))) argument
372 #define MACIO_BIS(r,v) (MACIO_OUT32((r), MACIO_IN32(r) | (v))) argument
373 #define MACIO_BIC(r,v) (MACIO_OUT32((r), MACIO_IN32(r) & ~(v))) argument
374 #define MACIO_IN8(r) (in_8(MACIO_FCR8(macio,r))) argument
375 #define MACIO_OUT8(r,v) (out_8(MACIO_FCR8(macio,r), (v))) argument
389 #define UN_REG(r) (uninorth_base + ((r) >> 2)) argument
390 #define UN_IN(r) (in_be32(UN_REG(r))) argument
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/arch/arm64/include/asm/
Dkvm_hyp.h30 #define read_sysreg_el0(r) read_sysreg_s(r##_EL02) argument
31 #define write_sysreg_el0(v,r) write_sysreg_s(v, r##_EL02) argument
32 #define read_sysreg_el1(r) read_sysreg_s(r##_EL12) argument
33 #define write_sysreg_el1(v,r) write_sysreg_s(v, r##_EL12) argument
34 #define read_sysreg_el2(r) read_sysreg_s(r##_EL1) argument
35 #define write_sysreg_el2(v,r) write_sysreg_s(v, r##_EL1) argument
45 #define read_sysreg_elx(r,nvh,vh) \ argument
48 asm volatile(ALTERNATIVE(__mrs_s("%0", r##nvh), \
49 __mrs_s("%0", r##vh), \
55 #define write_sysreg_elx(v,r,nvh,vh) \ argument
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/arch/arm/common/
Dlocomo.c169 unsigned int r; in locomo_mask_irq() local
170 r = locomo_readl(lchip->base + LOCOMO_ICR); in locomo_mask_irq()
171 r &= ~(0x0010 << (d->irq - lchip->irq_base)); in locomo_mask_irq()
172 locomo_writel(r, lchip->base + LOCOMO_ICR); in locomo_mask_irq()
178 unsigned int r; in locomo_unmask_irq() local
179 r = locomo_readl(lchip->base + LOCOMO_ICR); in locomo_unmask_irq()
180 r |= (0x0010 << (d->irq - lchip->irq_base)); in locomo_unmask_irq()
181 locomo_writel(r, lchip->base + LOCOMO_ICR); in locomo_unmask_irq()
320 unsigned long r; in locomo_resume() local
339 r = locomo_readl(lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC); in locomo_resume()
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/arch/mips/include/asm/
Dcop2.h19 #define cop2_save(r) octeon_cop2_save(&(r)->thread.cp2) argument
20 #define cop2_restore(r) octeon_cop2_restore(&(r)->thread.cp2) argument
29 #define cop2_save(r) do { (void)(r); } while (0) argument
30 #define cop2_restore(r) do { (void)(r); } while (0) argument
36 #define cop2_save(r) do { (void)(r); } while (0) argument
37 #define cop2_restore(r) do { (void)(r); } while (0) argument
/arch/x86/platform/olpc/
Dolpc-xo1-sci.c176 int r; in process_sci_queue() local
180 r = olpc_ec_sci_query(&data); in process_sci_queue()
181 if (r || !data) in process_sci_queue()
202 if (r) in process_sci_queue()
317 int r; in setup_sci_interrupt() local
348 r = request_irq(sci_irq, xo1_sci_intr, 0, DRV_NAME, pdev); in setup_sci_interrupt()
349 if (r) in setup_sci_interrupt()
352 return r; in setup_sci_interrupt()
357 int r; in setup_ec_sci() local
359 r = gpio_request(OLPC_GPIO_ECSCI, "OLPC-ECSCI"); in setup_ec_sci()
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/arch/x86/pci/
Di386.c212 struct resource *r; in pcibios_allocate_bridge_resources() local
215 r = &dev->resource[idx]; in pcibios_allocate_bridge_resources()
216 if (!r->flags) in pcibios_allocate_bridge_resources()
218 if (r->parent) /* Already allocated */ in pcibios_allocate_bridge_resources()
220 if (!r->start || pci_claim_bridge_resource(dev, idx) < 0) { in pcibios_allocate_bridge_resources()
227 r->start = r->end = 0; in pcibios_allocate_bridge_resources()
228 r->flags = 0; in pcibios_allocate_bridge_resources()
253 struct resource *r; in pcibios_allocate_dev_resources() local
265 r = &dev->resource[idx]; in pcibios_allocate_dev_resources()
266 if (r->parent) /* Already allocated */ in pcibios_allocate_dev_resources()
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Dirq.c62 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
964 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) in intel_router_probe() argument
978 r->name = "PCEB/ESC"; in intel_router_probe()
979 r->get = pirq_esc_get; in intel_router_probe()
980 r->set = pirq_esc_set; in intel_router_probe()
1023 r->name = "PIIX/ICH"; in intel_router_probe()
1024 r->get = pirq_piix_get; in intel_router_probe()
1025 r->set = pirq_piix_set; in intel_router_probe()
1028 r->name = "PSC/IB"; in intel_router_probe()
1029 r->get = pirq_ib_get; in intel_router_probe()
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/arch/powerpc/kvm/
Dpowerpc.c81 int r; in kvmppc_prepare_to_enter() local
97 r = -EINTR; in kvmppc_prepare_to_enter()
118 r = kvmppc_core_check_requests(vcpu); in kvmppc_prepare_to_enter()
120 if (r > 0) in kvmppc_prepare_to_enter()
137 return r; in kvmppc_prepare_to_enter()
165 int r; in kvmppc_kvm_pv() local
227 r = EV_SUCCESS; in kvmppc_kvm_pv()
231 r = EV_SUCCESS; in kvmppc_kvm_pv()
239 r = EV_SUCCESS; in kvmppc_kvm_pv()
243 r = EV_UNIMPLEMENTED; in kvmppc_kvm_pv()
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/arch/arm64/kvm/hyp/include/nvhe/
Drefcount.h67 #define hyp_refcount_inc(r) __hyp_refcount_fetch_add(&(r), sizeof(r), 1) argument
68 #define hyp_refcount_dec(r) __hyp_refcount_fetch_add(&(r), sizeof(r), -1) argument
69 #define hyp_refcount_get(r) READ_ONCE(r) argument
70 #define hyp_refcount_set(r, v) do { \ argument
71 typeof(r) *__rp = &(r); \
/arch/arm/mach-omap2/
Dboard-n8x0.c245 int r; in n8x0_mmc_set_bus_mode() local
253 r = menelaus_set_mmc_opendrain(slot, 1); in n8x0_mmc_set_bus_mode()
256 r = menelaus_set_mmc_opendrain(slot, 0); in n8x0_mmc_set_bus_mode()
261 if (r != 0 && printk_ratelimit()) in n8x0_mmc_set_bus_mode()
264 return r; in n8x0_mmc_set_bus_mode()
305 int r, bit, *openp; in n8x0_mmc_late_init() local
310 r = menelaus_set_slot_sel(1); in n8x0_mmc_late_init()
311 if (r < 0) in n8x0_mmc_late_init()
312 return r; in n8x0_mmc_late_init()
319 r = menelaus_set_mmc_slot(2, 0, vs2sel, 1); in n8x0_mmc_late_init()
[all …]
/arch/arm64/kvm/
Dsys_regs.h137 const struct sys_reg_desc *r) in reset_unknown() argument
139 BUG_ON(!r->reg); in reset_unknown()
140 BUG_ON(r->reg >= NR_SYS_REGS); in reset_unknown()
141 __vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL; in reset_unknown()
142 return __vcpu_sys_reg(vcpu, r->reg); in reset_unknown()
145 static inline u64 reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) in reset_val() argument
147 BUG_ON(!r->reg); in reset_val()
148 BUG_ON(r->reg >= NR_SYS_REGS); in reset_val()
149 __vcpu_sys_reg(vcpu, r->reg) = r->val; in reset_val()
150 return __vcpu_sys_reg(vcpu, r->reg); in reset_val()
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/arch/powerpc/sysdev/
Dtsi108_dev.c72 struct resource r[2]; in tsi108_eth_of_init() local
78 memset(r, 0, sizeof(r)); in tsi108_eth_of_init()
81 ret = of_address_to_resource(np, 0, &r[0]); in tsi108_eth_of_init()
83 __func__, r[0].name, &r[0]); in tsi108_eth_of_init()
87 r[1].name = "tx"; in tsi108_eth_of_init()
88 r[1].start = irq_of_parse_and_map(np, 0); in tsi108_eth_of_init()
89 r[1].end = irq_of_parse_and_map(np, 0); in tsi108_eth_of_init()
90 r[1].flags = IORESOURCE_IRQ; in tsi108_eth_of_init()
92 __func__, r[1].name, &r[1]); in tsi108_eth_of_init()
95 platform_device_register_simple("tsi-ethernet", i++, &r[0], in tsi108_eth_of_init()
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/arch/riscv/kvm/
Dvm.c32 int r; in kvm_arch_init_vm() local
34 r = kvm_riscv_gstage_alloc_pgd(kvm); in kvm_arch_init_vm()
35 if (r) in kvm_arch_init_vm()
36 return r; in kvm_arch_init_vm()
38 r = kvm_riscv_gstage_vmid_init(kvm); in kvm_arch_init_vm()
39 if (r) { in kvm_arch_init_vm()
41 return r; in kvm_arch_init_vm()
122 int r = -EINVAL; in kvm_set_routing_entry() local
144 r = 0; in kvm_set_routing_entry()
146 return r; in kvm_set_routing_entry()
[all …]
/arch/arm64/kvm/vgic/
Dvgic-kvm-device.c47 int r; in kvm_set_legacy_vgic_v2_addr() local
52 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2); in kvm_set_legacy_vgic_v2_addr()
53 if (!r) in kvm_set_legacy_vgic_v2_addr()
54 r = vgic_check_iorange(kvm, vgic->vgic_dist_base, dev_addr->addr, in kvm_set_legacy_vgic_v2_addr()
56 if (!r) in kvm_set_legacy_vgic_v2_addr()
60 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2); in kvm_set_legacy_vgic_v2_addr()
61 if (!r) in kvm_set_legacy_vgic_v2_addr()
62 r = vgic_check_iorange(kvm, vgic->vgic_cpu_base, dev_addr->addr, in kvm_set_legacy_vgic_v2_addr()
64 if (!r) in kvm_set_legacy_vgic_v2_addr()
68 r = -ENODEV; in kvm_set_legacy_vgic_v2_addr()
[all …]
/arch/sparc/kernel/
Dauxio_32.c33 struct resource r; in auxio_probe() local
66 r.flags = auxregs[0].which_io & 0xF; in auxio_probe()
67 r.start = auxregs[0].phys_addr; in auxio_probe()
68 r.end = auxregs[0].phys_addr + auxregs[0].reg_size - 1; in auxio_probe()
69 auxio_register = of_ioremap(&r, 0, auxregs[0].reg_size, "auxio"); in auxio_probe()
115 struct resource r; in auxio_power_probe() local
129 memset(&r, 0, sizeof(r)); in auxio_power_probe()
130 r.flags = regs.which_io & 0xF; in auxio_power_probe()
131 r.start = regs.phys_addr; in auxio_power_probe()
132 r.end = regs.phys_addr + regs.reg_size - 1; in auxio_power_probe()
[all …]

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