| /arch/nios2/include/asm/ |
| D | entry.h | 24 rdctl r24, estatus
25 andi r24, r24, ESTATUS_EU
26 beq r24, r0, 1f /* In supervisor mode, already on kernel stack */
28 movia r24, _current_thread /* Switch to current kernel stack */
29 ldw r24, 0(r24) /* using the thread_info */
30 addi r24, r24, THREAD_SIZE-PT_REGS_SIZE
31 stw sp, PT_SP(r24) /* Save user stack before changing */
32 mov sp, r24
35 1 : mov r24, sp
37 stw r24, PT_SP(sp)
[all …]
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| /arch/ia64/lib/ |
| D | flush.S | 40 shl r24=r23,r20 // r24: addresses for "fc.i" =
52 .Loop: fc.i r24 // issuable on M0 only
53 add r24=r21,r24 // we flush "stride size" bytes per iteration
94 shl r24=r23,r20 // r24: addresses for "fc" =
108 fc r24 // issuable on M0 only
109 add r24=r21,r24 // we flush "stride size" bytes per iteration
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| D | ip_fast_csum.S | 51 ld4 r24=[in0]
57 add r20=r20,r24
108 ld4 r24=[in0],4
118 add r18=r24,r25
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| /arch/hexagon/kernel/ |
| D | head.S | 28 r24.L = #LO(swapper_pg_dir)
29 r24.H = #HI(swapper_pg_dir)
41 r24 = sub(r24,r1); /* swapper_pg_dir - PAGE_OFFSET */ define
42 r24 = add(r24,r25); /* + PHYS_OFFSET */ define
44 r0 = r24; /* aka __pa(swapper_pg_dir) */
98 r0 = add(r1, r24); /* advance to 0xc0000000 entry */
113 r0 = r24;
156 r0 = r24
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| /arch/nios2/kernel/ |
| D | entry.S | 145 rdctl r24, status
147 and r24, r24, r9
148 wrctl status, r24
154 add r24, r9, r5
155 ldw r24, 0(r24)
156 jmp r24
164 ldwio r24, -4(ea) /* instruction that caused the exception */
165 srli r24, r24, 4
166 andi r24, r24, 0x7c
168 add r24, r24, r9
[all …]
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| D | head.S | 82 movia r24, inthandler
83 jmp r24
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| /arch/parisc/kernel/ |
| D | syscall.S | 151 depdi 0, 31, 32, %r24
207 STREG %r24, TASK_PT_GR24(%r1) /* 3rd argument */
359 LDREG TASK_PT_GR24(%r1), %r24
610 depdi 0, 31, 32, %r24
661 4: stw %r24, 0(%r26)
709 depdi 0, 31, 32, %r24
726 2: ldb 0(%r24), %r24
736 4: ldh 0(%r24), %r24
746 6: ldw 0(%r24), %r24
756 8: ldd 0(%r24), %r24
[all …]
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| D | sys_parisc32.c | 19 asmlinkage long sys32_unimplemented(int r26, int r25, int r24, int r23, in sys32_unimplemented() argument
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| /arch/parisc/include/asm/ |
| D | unistd.h | 76 #define K_LOAD_ARGS_3(r26,r25,r24) \ argument
77 register unsigned long __r24 __asm__("r24") = (unsigned long)(r24); \
79 #define K_LOAD_ARGS_4(r26,r25,r24,r23) \ argument
81 K_LOAD_ARGS_3(r26,r25,r24)
82 #define K_LOAD_ARGS_5(r26,r25,r24,r23,r22) \ argument
84 K_LOAD_ARGS_4(r26,r25,r24,r23)
85 #define K_LOAD_ARGS_6(r26,r25,r24,r23,r22,r21) \ argument
87 K_LOAD_ARGS_5(r26,r25,r24,r23,r22)
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| D | asmregs.h | 13 arg2: .reg %r24
57 r24: .reg %r24
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| /arch/powerpc/kernel/ |
| D | head_64.S | 154 mfmsr r24
155 ori r24,r24,MSR_RI
156 mtmsrd r24 /* RI on */
159 mr r24,r3
166 std r24,(ABS_ADDR(__secondary_hold_acknowledge, first_256B))(0)
179 mr r3,r24
307 mr r24,r3
313 mr r3,r24
338 mr r24,r3
346 mr r3,r24
[all …]
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| D | idle_book3s.S | 71 std r24,-8*12(r1)
116 ld r24,-8*12(r1)
179 std r24,-8*12(r1)
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| D | head_44x.S | 62 li r24,0 /* CPU number */
1001 mr r24,r3 /* CPU number */
1060 tlbre r24,r23,0
1102 tlbwe r24,r23,0
1158 rlwinm r24,r24,0,21,19 /* clear the "valid" bit */
1159 tlbwe r24,r23,0
1160 addi r24,0,0
1161 tlbwe r24,r23,1
1162 tlbwe r24,r23,2
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| /arch/powerpc/kexec/ |
| D | relocate_32.S | 112 addi r24, r6, 1 /* r24 will contain 1 or 2 */
151 tlbwe r3, r24, PPC44x_TLB_PAGEID
152 tlbwe r4, r24, PPC44x_TLB_XLAT
153 tlbwe r5, r24, PPC44x_TLB_ATTRIB
219 tlbwe r3, r24, PPC44x_TLB_PAGEID
246 tlbre r24, r23, 0 /* TLB Word 0 */
284 insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */
292 tlbwe r24, r3, 0
347 rlwinm r10, r24, 0, 22, 27
382 clrrwi r24, r24, 12 /* Clear the valid bit */
[all …]
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| /arch/microblaze/lib/ |
| D | uaccess_old.S | 23 7: lwi r24, r6, 0x0018 + offset; \
31 15: swi r24, r5, 0x0018 + offset; \
111 swi r24, r1, 32
134 lwi r24, r1, 32
154 lwi r24, r1, 32
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| /arch/ia64/kernel/ |
| D | minstate.h | 72 (pUStk) mov.m r24=ar.rnat; \
119 (pUStk) st8 [r17]=r24,16; /* save ar.rnat */ \
182 .mem.offset 0,0; st8.spill [r2]=r24,16; \
196 adds r24=PT(B6)-PT(F7),r3; \
208 st8 [r24]=r18,16; /* b6 */ \
211 st8 [r24]=r9; /* ar.csd */ \
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| D | ivt.S | 187 ITC_I_AND_D(p10, p11, r18, r24) // insert the instruction TLB entry and
190 MOV_TO_IFA(r22, r24)
193 MOV_TO_ITIR(p8, r25, r24) // change to default page-size for VHPT
201 adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23
203 ITC_D(p7, r24, r25)
385 mov r24=PERCPU_ADDR
398 cmp.ge p10,p11=r16,r24 // access to per_cpu_data?
413 MOV_TO_ITIR(p10, r25, r24)
422 MOV_TO_IPSR(p6, r21, r24)
556 mov r24=PAGE_SHIFT<<2
[all …]
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| D | relocate_kernel.S | 73 mov r24=r0
79 cmp.ltu p6,p7=r24,r19
89 add r24=1,r24
292 st8 [in0]=r24, 8 // r24
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| D | fsys.S | 220 add r24 = IA64_CLKSRC_MULT_OFFSET,r20
225 ld4 r3 = [r24] // clocksource mult value
232 ld8 r24 = [r26] // get clksrc_cycle_last value
245 sub r10 = r2,r24 // current_cycle - last_cycle
247 (p6) sub r10 = r25,r24 // time we got was less than last_cycle
254 (p7) sub r10 = r3,r24 // then use new last_cycle instead
494 mov.m r24=ar.rnat // M2 (5 cyc) read ar.rnat (dual-issues!)
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| /arch/openrisc/kernel/ |
| D | head.S | 560 CLEAR_GPR(r24)
591 LOAD_SYMBOL_2_GPR(r24, __bss_start)
593 tophys(r28,r24)
595 CLEAR_GPR(r24)
659 LOAD_SYMBOL_2_GPR(r24, or1k_early_setup)
660 l.jalr r24
688 CLEAR_GPR(r24)
828 l.mfspr r24,r0,SPR_UPR
829 l.andi r26,r24,SPR_UPR_ICP
846 l.mfspr r24,r0,SPR_ICCFGR
[all …]
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| /arch/arc/include/asm/ |
| D | unwind.h | 38 unsigned long r24; member
97 PTREGS_INFO(r24), \
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| /arch/alpha/include/uapi/asm/ |
| D | ptrace.h | 35 unsigned long r24; member
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| /arch/loongarch/power/ |
| D | suspend_asm.S | 25 st.d $r24, sp, PT_R24
46 ld.d $r24, sp, PT_R24
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| /arch/arc/include/uapi/asm/ |
| D | ptrace.h | 45 unsigned long r25, r24, r23, r22, r21, r20; member
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| /arch/hexagon/include/asm/ |
| D | processor.h | 110 unsigned long r24; member
|