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Searched refs:reg_val (Results 1 – 13 of 13) sorted by relevance

/arch/riscv/kvm/
Dvcpu_onereg.c127 unsigned long reg_val; in kvm_riscv_vcpu_get_reg_config() local
134 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK; in kvm_riscv_vcpu_get_reg_config()
139 reg_val = riscv_cbom_block_size; in kvm_riscv_vcpu_get_reg_config()
144 reg_val = riscv_cboz_block_size; in kvm_riscv_vcpu_get_reg_config()
147 reg_val = vcpu->arch.mvendorid; in kvm_riscv_vcpu_get_reg_config()
150 reg_val = vcpu->arch.marchid; in kvm_riscv_vcpu_get_reg_config()
153 reg_val = vcpu->arch.mimpid; in kvm_riscv_vcpu_get_reg_config()
156 reg_val = satp_mode >> SATP_MODE_SHIFT; in kvm_riscv_vcpu_get_reg_config()
162 if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_config()
176 unsigned long i, isa_ext, reg_val; in kvm_riscv_vcpu_set_reg_config() local
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Dvcpu_sbi.c137 unsigned long reg_val) in riscv_vcpu_set_sbi_ext_single() argument
146 if (reg_val != 1 && reg_val != 0) in riscv_vcpu_set_sbi_ext_single()
164 if (!reg_val) in riscv_vcpu_set_sbi_ext_single()
173 unsigned long *reg_val) in riscv_vcpu_get_sbi_ext_single() argument
198 *reg_val = scontext->ext_status[sext->ext_idx] != in riscv_vcpu_get_sbi_ext_single()
206 unsigned long reg_val, bool enable) in riscv_vcpu_set_sbi_ext_multi() argument
213 for_each_set_bit(i, &reg_val, BITS_PER_LONG) { in riscv_vcpu_set_sbi_ext_multi()
226 unsigned long *reg_val) in riscv_vcpu_get_sbi_ext_multi() argument
241 *reg_val |= KVM_REG_RISCV_SBI_MULTI_MASK(ext_id); in riscv_vcpu_get_sbi_ext_multi()
255 unsigned long reg_val, reg_subtype; in kvm_riscv_vcpu_set_reg_sbi_ext() local
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Dvcpu_fp.c87 void *reg_val; in kvm_riscv_vcpu_get_reg_fp() local
94 reg_val = &cntx->fp.f.fcsr; in kvm_riscv_vcpu_get_reg_fp()
97 reg_val = &cntx->fp.f.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp()
105 reg_val = &cntx->fp.d.fcsr; in kvm_riscv_vcpu_get_reg_fp()
110 reg_val = &cntx->fp.d.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp()
116 if (copy_to_user(uaddr, reg_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_fp()
132 void *reg_val; in kvm_riscv_vcpu_set_reg_fp() local
139 reg_val = &cntx->fp.f.fcsr; in kvm_riscv_vcpu_set_reg_fp()
142 reg_val = &cntx->fp.f.f[reg_num]; in kvm_riscv_vcpu_set_reg_fp()
150 reg_val = &cntx->fp.d.fcsr; in kvm_riscv_vcpu_set_reg_fp()
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Dvcpu_timer.c168 u64 reg_val; in kvm_riscv_vcpu_get_reg_timer() local
177 reg_val = riscv_timebase; in kvm_riscv_vcpu_get_reg_timer()
180 reg_val = kvm_riscv_current_cycles(gt); in kvm_riscv_vcpu_get_reg_timer()
183 reg_val = t->next_cycles; in kvm_riscv_vcpu_get_reg_timer()
186 reg_val = (t->next_set) ? KVM_RISCV_TIMER_STATE_ON : in kvm_riscv_vcpu_get_reg_timer()
193 if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_timer()
208 u64 reg_val; in kvm_riscv_vcpu_set_reg_timer() local
216 if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_timer()
221 if (reg_val != riscv_timebase) in kvm_riscv_vcpu_set_reg_timer()
225 gt->time_delta = reg_val - get_cycles64(); in kvm_riscv_vcpu_set_reg_timer()
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/arch/powerpc/platforms/powernv/
Dopal-fadump.h83 __be64 reg_val; member
88 u64 reg_val) in opal_fadump_set_regval_regnum() argument
92 regs->gpr[reg_num] = reg_val; in opal_fadump_set_regval_regnum()
98 regs->ctr = reg_val; in opal_fadump_set_regval_regnum()
101 regs->link = reg_val; in opal_fadump_set_regval_regnum()
104 regs->xer = reg_val; in opal_fadump_set_regval_regnum()
107 regs->dar = reg_val; in opal_fadump_set_regval_regnum()
110 regs->dsisr = reg_val; in opal_fadump_set_regval_regnum()
113 regs->nip = reg_val; in opal_fadump_set_regval_regnum()
116 regs->msr = reg_val; in opal_fadump_set_regval_regnum()
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/arch/mips/pci/
Dfixup-malta.c70 unsigned char reg_val; in malta_piix_func0_fixup() local
84 pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, &reg_val); in malta_piix_func0_fixup()
85 if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE) in malta_piix_func0_fixup()
88 pci_irq[PCIA+i] = piixirqmap[reg_val & in malta_piix_func0_fixup()
98 pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val); in malta_piix_func0_fixup()
99 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | in malta_piix_func0_fixup()
109 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val); in malta_piix_func0_fixup()
110 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT; in malta_piix_func0_fixup()
111 pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val); in malta_piix_func0_fixup()
124 unsigned char reg_val; in malta_piix_func1_fixup() local
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/arch/arm/mach-qcom/
Dplatsmp.c84 u32 reg_val; in cortex_a7_release_secondary() local
103 reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP; in cortex_a7_release_secondary()
104 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
111 reg_val &= ~CORE_MEM_CLAMP; in cortex_a7_release_secondary()
112 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
113 reg_val |= L2DT_SLP; in cortex_a7_release_secondary()
114 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
117 reg_val = (reg_val | BIT(17)) & ~CLAMP; in cortex_a7_release_secondary()
118 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
122 reg_val &= ~(CORE_RST | COREPOR_RST); in cortex_a7_release_secondary()
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/arch/x86/hyperv/
Dhv_apic.c39 u64 reg_val; in hv_apic_icr_read() local
41 rdmsrl(HV_X64_MSR_ICR, reg_val); in hv_apic_icr_read()
42 return reg_val; in hv_apic_icr_read()
47 u64 reg_val; in hv_apic_icr_write() local
49 reg_val = SET_XAPIC_DEST_FIELD(id); in hv_apic_icr_write()
50 reg_val = reg_val << 32; in hv_apic_icr_write()
51 reg_val |= low; in hv_apic_icr_write()
53 wrmsrl(HV_X64_MSR_ICR, reg_val); in hv_apic_icr_write()
58 u32 reg_val, hi; in hv_apic_read() local
62 rdmsr(HV_X64_MSR_EOI, reg_val, hi); in hv_apic_read()
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/arch/powerpc/platforms/pseries/
Drtas-fadump.c257 static void __init rtas_fadump_set_regval(struct pt_regs *regs, u64 reg_id, u64 reg_val) in rtas_fadump_set_regval() argument
263 regs->gpr[i] = (unsigned long)reg_val; in rtas_fadump_set_regval()
265 regs->nip = (unsigned long)reg_val; in rtas_fadump_set_regval()
267 regs->msr = (unsigned long)reg_val; in rtas_fadump_set_regval()
269 regs->ctr = (unsigned long)reg_val; in rtas_fadump_set_regval()
271 regs->link = (unsigned long)reg_val; in rtas_fadump_set_regval()
273 regs->xer = (unsigned long)reg_val; in rtas_fadump_set_regval()
275 regs->ccr = (unsigned long)reg_val; in rtas_fadump_set_regval()
277 regs->dar = (unsigned long)reg_val; in rtas_fadump_set_regval()
279 regs->dsisr = (unsigned long)reg_val; in rtas_fadump_set_regval()
/arch/mips/include/asm/
Dmips-cps.h75 uint##sz##_t reg_val = read_##unit##_##name(); \
76 reg_val &= ~mask; \
77 reg_val |= val; \
78 write_##unit##_##name(reg_val); \
/arch/mips/kernel/
Dtraps.c1835 unsigned int reg_val; in cache_parity_error() local
1840 reg_val = read_c0_cacheerr(); in cache_parity_error()
1841 printk("c0_cacheerr == %08x\n", reg_val); in cache_parity_error()
1844 reg_val & (1<<30) ? "secondary" : "primary", in cache_parity_error()
1845 reg_val & (1<<31) ? "data" : "insn"); in cache_parity_error()
1849 reg_val & (1<<29) ? "ED " : "", in cache_parity_error()
1850 reg_val & (1<<28) ? "ET " : "", in cache_parity_error()
1851 reg_val & (1<<27) ? "ES " : "", in cache_parity_error()
1852 reg_val & (1<<26) ? "EE " : "", in cache_parity_error()
1853 reg_val & (1<<25) ? "EB " : "", in cache_parity_error()
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/arch/arm/plat-orion/
Dgpio.c496 u32 reg_val; in orion_gpio_unmask_irq() local
500 reg_val = irq_reg_readl(gc, ct->regs.mask); in orion_gpio_unmask_irq()
501 reg_val |= mask; in orion_gpio_unmask_irq()
502 irq_reg_writel(gc, reg_val, ct->regs.mask); in orion_gpio_unmask_irq()
511 u32 reg_val; in orion_gpio_mask_irq() local
514 reg_val = irq_reg_readl(gc, ct->regs.mask); in orion_gpio_mask_irq()
515 reg_val &= ~mask; in orion_gpio_mask_irq()
516 irq_reg_writel(gc, reg_val, ct->regs.mask); in orion_gpio_mask_irq()
/arch/sparc/include/asm/
Dhypervisor.h3446 unsigned long *reg_val);
3448 unsigned long reg_val);
3456 unsigned long *reg_val);
3458 unsigned long reg_val);
3467 unsigned long *reg_val);
3469 unsigned long reg_val);