| /drivers/gpu/drm/amd/display/modules/color/ |
| D | color_gamma.h | 68 int A3[3]; member
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| D | color_gamma.c | 1773 regamma->coeff.A3[i], 1000); in calculate_user_regamma_coeff()
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| /drivers/gpu/drm/i915/ |
| D | intel_step.h | 30 func(A3) \
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| /drivers/pinctrl/aspeed/ |
| D | pinctrl-aspeed-g5.c | 1239 #define A3 166 macro
1240 SIG_EXPR_LIST_DECL_SINGLE(A3, GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
1241 SIG_EXPR_LIST_DECL_SINGLE(A3, RMII1RXD0, RMII1, RMII1_DESC);
1242 SIG_EXPR_LIST_DECL_SINGLE(A3, RGMII1RXD0, RGMII1);
1243 PIN_DECL_(A3, SIG_EXPR_LIST_PTR(A3, GPIOU6), SIG_EXPR_LIST_PTR(A3, RMII1RXD0),
1244 SIG_EXPR_LIST_PTR(A3, RGMII1RXD0));
1267 FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7);
1268 FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5);
1916 ASPEED_PINCTRL_PIN(A3),
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| D | pinctrl-aspeed-g6.c | 1319 #define A3 211 macro
1320 SIG_EXPR_LIST_DECL_SESG(A3, RGMII1TXD1, RGMII1, SIG_DESC_SET(SCU400, 3),
1322 SIG_EXPR_LIST_DECL_SESG(A3, RMII1TXD1, RMII1, SIG_DESC_SET(SCU400, 3),
1324 PIN_DECL_2(A3, GPIO18A3, RGMII1TXD1, RMII1TXD1);
1376 FUNC_GROUP_DECL(RGMII1, C6, D6, D5, A3, C5, E6, B3, A2, B2, B1, C4, E5);
1377 FUNC_GROUP_DECL(RMII1, C6, D6, D5, A3, B3, B2, B1, C4, E5);
1653 ASPEED_PINCTRL_PIN(A3),
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| D | pinctrl-aspeed-g4.c | 106 #define A3 6 macro
107 SIG_EXPR_LIST_DECL_SINGLE(A3, MDC2, MDIO2, MDIO2_DESC);
108 SIG_EXPR_LIST_DECL_SINGLE(A3, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6));
109 PIN_DECL_2(A3, GPIOA6, MDC2, TIMER7);
111 FUNC_GROUP_DECL(TIMER7, A3);
119 FUNC_GROUP_DECL(MDIO2, A3, D5);
1921 ASPEED_PINCTRL_PIN(A3),
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| /drivers/media/i2c/ |
| D | adv7511-v4l2.c | 288 u16 A1, u16 A2, u16 A3, u16 A4, in adv7511_csc_coeff() argument
297 adv7511_wr_and_or(sd, 0x1c, 0xe0, A3>>8); in adv7511_csc_coeff()
298 adv7511_wr(sd, 0x1d, A3); in adv7511_csc_coeff()
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| D | adv7842.c | 1751 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8); in sdp_csc_coeff()
1752 sdp_io_write(sd, 0xe5, c->A3); in sdp_csc_coeff()
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| /drivers/pinctrl/renesas/ |
| D | pfc-r8a77970.c | 167 #define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
407 PINMUX_IPSR_GPSR(IP0_15_12, A3),
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| D | pfc-r8a77980.c | 201 #define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) …
479 PINMUX_IPSR_GPSR(IP0_15_12, A3),
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| D | pfc-r8a77990.c | 107 #define GPSR1_3 F_(A3, IP3_11_8)
240 #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(…
684 PINMUX_IPSR_GPSR(IP3_11_8, A3),
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| D | pfc-sh7734.c | 605 PINMUX_IPSR_GPSR(IP0_7_6, A3),
1370 GPIO_FN(A3), GPIO_FN(ST0_VLD), GPIO_FN(LCD_DATA3_A),
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| D | pfc-r8a77951.c | 124 #define GPSR1_3 F_(A3, IP2_11_8)
272 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB…
757 PINMUX_IPSR_GPSR(IP2_11_8, A3),
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| D | pfc-r8a7796.c | 129 #define GPSR1_3 F_(A3, IP2_11_8)
277 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB…
761 PINMUX_IPSR_GPSR(IP2_11_8, A3),
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| D | pfc-r8a77965.c | 129 #define GPSR1_3 F_(A3, IP2_11_8)
277 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB…
763 PINMUX_IPSR_GPSR(IP2_11_8, A3),
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| D | pfc-r8a779a0.c | 360 #define IP0SR1_15_12 FM(HRTS0_N) FM(RTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_…
804 PINMUX_IPSR_GPSR(IP0SR1_15_12, A3),
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| D | pfc-r8a7792.c | 376 PINMUX_SINGLE(A3),
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| D | pfc-sh7264.c | 1283 GPIO_FN(A3),
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| D | pfc-r8a73a4.c | 339 F1(A3), F2(MMCD1_0), IRQ(38),
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| D | pfc-sh7757.c | 1646 GPIO_FN(A3),
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| D | pfc-r8a77470.c | 692 PINMUX_IPSR_GPSR(IP4_19_16, A3),
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| D | pfc-sh7269.c | 1721 GPIO_FN(A3),
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| D | pfc-r8a7778.c | 533 PINMUX_SINGLE(A3),
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| D | pfc-r8a7794.c | 838 PINMUX_IPSR_GPSR(IP1_26, A3),
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| D | pfc-r8a7790.c | 913 PINMUX_IPSR_GPSR(IP2_5_3, A3),
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