1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef AMDGPU_DOORBELL_H 25 #define AMDGPU_DOORBELL_H 26 27 /* 28 * GPU doorbell structures, functions & helpers 29 */ 30 struct amdgpu_doorbell { 31 /* doorbell mmio */ 32 resource_size_t base; 33 resource_size_t size; 34 35 /* Number of doorbells reserved for amdgpu kernel driver */ 36 u32 num_kernel_doorbells; 37 38 /* Kernel doorbells */ 39 struct amdgpu_bo *kernel_doorbells; 40 41 /* For CPU access of doorbells */ 42 uint32_t *cpu_addr; 43 }; 44 45 /* Reserved doorbells for amdgpu (including multimedia). 46 * KFD can use all the rest in the 2M doorbell bar. 47 * For asic before vega10, doorbell is 32-bit, so the 48 * index/offset is in dword. For vega10 and after, doorbell 49 * can be 64-bit, so the index defined is in qword. 50 */ 51 struct amdgpu_doorbell_index { 52 uint32_t kiq; 53 uint32_t mec_ring0; 54 uint32_t mec_ring1; 55 uint32_t mec_ring2; 56 uint32_t mec_ring3; 57 uint32_t mec_ring4; 58 uint32_t mec_ring5; 59 uint32_t mec_ring6; 60 uint32_t mec_ring7; 61 uint32_t userqueue_start; 62 uint32_t userqueue_end; 63 uint32_t gfx_ring0; 64 uint32_t gfx_ring1; 65 uint32_t gfx_userqueue_start; 66 uint32_t gfx_userqueue_end; 67 uint32_t sdma_engine[16]; 68 uint32_t mes_ring0; 69 uint32_t mes_ring1; 70 uint32_t ih; 71 union { 72 struct { 73 uint32_t vcn_ring0_1; 74 uint32_t vcn_ring2_3; 75 uint32_t vcn_ring4_5; 76 uint32_t vcn_ring6_7; 77 } vcn; 78 struct { 79 uint32_t uvd_ring0_1; 80 uint32_t uvd_ring2_3; 81 uint32_t uvd_ring4_5; 82 uint32_t uvd_ring6_7; 83 uint32_t vce_ring0_1; 84 uint32_t vce_ring2_3; 85 uint32_t vce_ring4_5; 86 uint32_t vce_ring6_7; 87 } uvd_vce; 88 }; 89 uint32_t first_non_cp; 90 uint32_t last_non_cp; 91 uint32_t max_assignment; 92 /* Per engine SDMA doorbell size in dword */ 93 uint32_t sdma_doorbell_range; 94 /* Per xcc doorbell size for KIQ/KCQ */ 95 uint32_t xcc_doorbell_range; 96 }; 97 98 enum AMDGPU_DOORBELL_ASSIGNMENT { 99 AMDGPU_DOORBELL_KIQ = 0x000, 100 AMDGPU_DOORBELL_HIQ = 0x001, 101 AMDGPU_DOORBELL_DIQ = 0x002, 102 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 103 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 104 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 105 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 106 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 107 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 108 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 109 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 110 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 111 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 112 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 113 AMDGPU_DOORBELL_IH = 0x1E8, 114 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 115 AMDGPU_DOORBELL_INVALID = 0xFFFF 116 }; 117 118 enum AMDGPU_VEGA20_DOORBELL_ASSIGNMENT { 119 120 /* Compute + GFX: 0~255 */ 121 AMDGPU_VEGA20_DOORBELL_KIQ = 0x000, 122 AMDGPU_VEGA20_DOORBELL_HIQ = 0x001, 123 AMDGPU_VEGA20_DOORBELL_DIQ = 0x002, 124 AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003, 125 AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004, 126 AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005, 127 AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006, 128 AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007, 129 AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008, 130 AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009, 131 AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A, 132 AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B, 133 AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A, 134 AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B, 135 /* SDMA:256~335*/ 136 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100, 137 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A, 138 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114, 139 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E, 140 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128, 141 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132, 142 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C, 143 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146, 144 /* IH: 376~391 */ 145 AMDGPU_VEGA20_DOORBELL_IH = 0x178, 146 /* MMSCH: 392~407 147 * overlap the doorbell assignment with VCN as they are mutually exclusive 148 * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD 149 */ 150 AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */ 151 AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189, 152 AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A, 153 AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B, 154 155 AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */ 156 AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D, 157 AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E, 158 AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F, 159 160 AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188, 161 AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189, 162 AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A, 163 AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B, 164 165 AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C, 166 AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D, 167 AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E, 168 AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F, 169 170 AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0, 171 AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7, 172 173 /* kiq/kcq from second XCD. Max 8 XCDs */ 174 AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START = 0x190, 175 /* 8 compute rings per GC. Max to 0x1CE */ 176 AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START = 0x197, 177 178 /* AID1 SDMA: 0x1D0 ~ 0x1F7 */ 179 AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START = 0x1D0, 180 181 AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x1F7, 182 AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF 183 }; 184 185 enum AMDGPU_NAVI10_DOORBELL_ASSIGNMENT { 186 187 /* Compute + GFX: 0~255 */ 188 AMDGPU_NAVI10_DOORBELL_KIQ = 0x000, 189 AMDGPU_NAVI10_DOORBELL_HIQ = 0x001, 190 AMDGPU_NAVI10_DOORBELL_DIQ = 0x002, 191 AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 0x003, 192 AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 0x004, 193 AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 0x005, 194 AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 0x006, 195 AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 0x007, 196 AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 0x008, 197 AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 0x009, 198 AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 0x00A, 199 AMDGPU_NAVI10_DOORBELL_MES_RING0 = 0x00B, 200 AMDGPU_NAVI10_DOORBELL_MES_RING1 = 0x00C, 201 AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 0x00D, 202 AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A, 203 AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B, 204 AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C, 205 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START = 0x08D, 206 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END = 0x0FF, 207 208 /* SDMA:256~335*/ 209 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100, 210 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A, 211 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = 0x114, 212 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = 0x11E, 213 /* IH: 376~391 */ 214 AMDGPU_NAVI10_DOORBELL_IH = 0x178, 215 /* MMSCH: 392~407 216 * overlap the doorbell assignment with VCN as they are mutually exclusive 217 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 218 */ 219 AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 220 AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 0x189, 221 AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A, 222 AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B, 223 224 AMDGPU_NAVI10_DOORBELL64_VCN8_9 = 0x18C, 225 AMDGPU_NAVI10_DOORBELL64_VCNa_b = 0x18D, 226 AMDGPU_NAVI10_DOORBELL64_VCNc_d = 0x18E, 227 AMDGPU_NAVI10_DOORBELL64_VCNe_f = 0x18F, 228 229 AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0, 230 AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VCNe_f, 231 232 AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 0x18F, 233 AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF 234 }; 235 236 /* 237 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 238 */ 239 enum AMDGPU_DOORBELL64_ASSIGNMENT { 240 /* 241 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 242 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 243 * Compute related doorbells are allocated from 0x00 to 0x8a 244 */ 245 246 247 /* kernel scheduling */ 248 AMDGPU_DOORBELL64_KIQ = 0x00, 249 250 /* HSA interface queue and debug queue */ 251 AMDGPU_DOORBELL64_HIQ = 0x01, 252 AMDGPU_DOORBELL64_DIQ = 0x02, 253 254 /* Compute engines */ 255 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 256 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 257 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 258 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 259 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 260 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 261 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 262 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 263 264 /* User queue doorbell range (128 doorbells) */ 265 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 266 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 267 268 /* Graphics engine */ 269 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 270 271 /* 272 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf 273 * Graphics voltage island aperture 1 274 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive 275 */ 276 277 /* For vega10 sriov, the sdma doorbell must be fixed as follow 278 * to keep the same setting with host driver, or it will 279 * happen conflicts 280 */ 281 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 282 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 283 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 284 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 285 286 /* Interrupt handler */ 287 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 288 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 289 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 290 291 /* VCN engine use 32 bits doorbell */ 292 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 293 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 294 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 295 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 296 297 /* overlap the doorbell assignment with VCN as they are mutually exclusive 298 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 299 */ 300 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 301 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 302 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 303 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 304 305 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 306 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 307 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 308 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 309 310 AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0, 311 AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7, 312 313 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 314 AMDGPU_DOORBELL64_INVALID = 0xFFFF 315 }; 316 317 enum AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 { 318 319 /* XCC0: 0x00 ~20, XCC1: 20 ~ 2F ... */ 320 321 /* KIQ/HIQ/DIQ */ 322 AMDGPU_DOORBELL_LAYOUT1_KIQ_START = 0x000, 323 AMDGPU_DOORBELL_LAYOUT1_HIQ = 0x001, 324 AMDGPU_DOORBELL_LAYOUT1_DIQ = 0x002, 325 /* Compute: 0x08 ~ 0x20 */ 326 AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START = 0x008, 327 AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END = 0x00F, 328 AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START = 0x010, 329 AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END = 0x01F, 330 AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE = 0x020, 331 332 /* SDMA: 0x100 ~ 0x19F */ 333 AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START = 0x100, 334 AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END = 0x19F, 335 /* IH: 0x1A0 ~ 0x1AF */ 336 AMDGPU_DOORBELL_LAYOUT1_IH = 0x1A0, 337 /* VCN: 0x1B0 ~ 0x1E8 */ 338 AMDGPU_DOORBELL_LAYOUT1_VCN_START = 0x1B0, 339 AMDGPU_DOORBELL_LAYOUT1_VCN_END = 0x1E8, 340 341 AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP = AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START, 342 AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP = AMDGPU_DOORBELL_LAYOUT1_VCN_END, 343 344 AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT = 0x1E8, 345 AMDGPU_DOORBELL_LAYOUT1_INVALID = 0xFFFF 346 }; 347 348 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 349 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 350 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 351 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 352 353 /* 354 * GPU doorbell aperture helpers function. 355 */ 356 int amdgpu_doorbell_init(struct amdgpu_device *adev); 357 void amdgpu_doorbell_fini(struct amdgpu_device *adev); 358 int amdgpu_doorbell_create_kernel_doorbells(struct amdgpu_device *adev); 359 uint32_t amdgpu_doorbell_index_on_bar(struct amdgpu_device *adev, 360 struct amdgpu_bo *db_bo, 361 uint32_t doorbell_index, 362 uint32_t db_size); 363 364 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 365 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 366 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 367 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 368 369 #endif 370