Home
last modified time | relevance | path

Searched refs:A_PL_CAUSE (Results 1 – 7 of 7) sorted by relevance

/drivers/net/ethernet/chelsio/cxgb/
Dtp.c117 writel(FPGA_PCIX_INTERRUPT_TP, tp->adapter->regs + A_PL_CAUSE); in t1_tp_intr_clear()
122 writel(F_PL_INTR_TP, tp->adapter->regs + A_PL_CAUSE); in t1_tp_intr_clear()
Dsubr.c210 u32 cause = readl(adapter->regs + A_PL_CAUSE); in fpga_slow_intr()
239 writel(cause, adapter->regs + A_PL_CAUSE); in fpga_slow_intr()
835 u32 pl_intr = readl(adapter->regs + A_PL_CAUSE); in t1_interrupts_clear()
838 adapter->regs + A_PL_CAUSE); in t1_interrupts_clear()
850 u32 cause = readl(adapter->regs + A_PL_CAUSE); in asic_slow_intr()
881 writel(cause, adapter->regs + A_PL_CAUSE); in asic_slow_intr()
882 readl(adapter->regs + A_PL_CAUSE); /* flush writes */ in asic_slow_intr()
Dpm3393.c227 pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE); in pm3393_interrupt_clear()
229 writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE); in pm3393_interrupt_clear()
Despi.c128 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); in t1_espi_intr_clear()
Dsge.c927 writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE); in t1_sge_intr_clear()
1644 writel(F_PL_INTR_EXT, adapter->regs + A_PL_CAUSE); in t1_interrupt_thread()
1659 writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE); in t1_interrupt()
Dcxgb2.c563 reg_block_dump(ap, buf, A_PL_ENABLE, A_PL_CAUSE); in get_regs()
Dregs.h1785 #define A_PL_CAUSE 0xa04 macro