Searched refs:BIT15 (Results 1 – 13 of 13) sorted by relevance
201 #define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is …229 #define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrupt 2 */
562 #define RRSR_MCS3 BIT15644 #define CAM_VALID BIT15700 #define IMR_TXFOVW BIT15 /* Transmit FIFO Overflow */718 #define IMR_TSF_BIT32_TOGGLE BIT15747 #define RCR_RSVD_BIT15 BIT15 /* Reserved */
32 #define BIT15 0x00008000 macro
390 #define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is se…418 #define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrupt 2 */
981 PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target); in rtw_bb_rf_gain_offset()
46 #define BIT15 0x00008000 macro
97 usConfig |= BIT15 | (KeyType << 2); in rtl92e_set_key()99 usConfig |= BIT15 | (KeyType << 2) | KeyIndex; in rtl92e_set_key()
107 #define IMR_TXFOVW BIT15
25 #define BIT15 0x00008000 macro
61 #define BIT15 0x00008000 macro
190 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)2045 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8)); in isr_rxdata()4120 val = BIT15 + BIT14 + BIT0; in async_mode()4172 val |= BIT15 + BIT13; in sync_mode()4175 case MGSL_MODE_BISYNC: val |= BIT15; break; in sync_mode()4247 val |= BIT15 + BIT13; in sync_mode()4250 case MGSL_MODE_BISYNC: val |= BIT15; break; in sync_mode()4356 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); in sync_mode()
373 #define RRSR_MCS3 BIT15
782 #define LPFC_SLI4_INTR15 BIT15