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Searched refs:BIT_2 (Results 1 – 25 of 25) sorted by relevance

/drivers/scsi/
Dqla1280.h19 #define BIT_2 0x4 macro
121 #define ISP_CFG0_1040 BIT_2 /* ISP1040 */
130 #define ISP_CFG1_BENAB BIT_2 /* Global Bus burst enable */
135 #define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */
140 #define RISC_INT BIT_2 /* RISC interrupt */
147 #define NV_DATA_OUT BIT_2
157 #define CDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
174 #define DDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
324 #define NV_START_BIT BIT_2
568 #define RF_BAD_HEADER BIT_2 /* Bad header. */
Dqla1280.c1114 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()
1680 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb); in qla1280_load_firmware_pio()
1694 #define CMD_ARGS (BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1698 #define CMD_ARGS (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1899 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
1913 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
2206 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla1280_nvram_config()
2240 status |= qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_2 | in qla1280_nvram_config()
2247 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]); in qla1280_nvram_config()
2261 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb); in qla1280_nvram_config()
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/drivers/scsi/qla2xxx/
Dqla_fw.h497 #define CF_DATA_SEG_DESCR_ENABLE BIT_2
539 #define TMF_DSD_LIST_ENABLE BIT_2
973 #define TCF_CLEAR_TASK_SET BIT_2
1002 #define AOF_ABTS_TIMEOUT BIT_2 /* Disable logout on ABTS timeout. */
1194 #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */
1257 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
1261 #define GPDX_LED_YELLOW_ON BIT_2
1460 #define CS_VF_SET_HOPS_OF_VPORTS BIT_2
1751 #define FSTATE_IS_DIAG_FW BIT_2
1767 #define VCO_DONT_RESET_UPDATE BIT_2
Dqla_def.h109 #define BIT_2 0x4 macro
231 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
418 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
535 #define SRB_LOGIN_SKIP_PRLI BIT_2
585 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
841 #define NVR_DATA_OUT BIT_2
1100 #define IOCTL_CMD BIT_2
1113 #define IOCTL_CMD BIT_2
1421 #define MBX_2 BIT_2
1530 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
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Dqla_nvme.h64 #define CF_DATA_SEG_DESCR_ENABLE BIT_2
Dqla_init.c1177 mb[1] = BIT_2 | BIT_3; in qla24xx_async_gnl()
4354 (ha->fw_attributes & BIT_2)) { in qla2x00_setup_chip()
4488 if (ha->fw_seriallink_options[3] & BIT_2) { in qla2x00_update_fw_options()
4492 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4496 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4514 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
5267 nv->firmware_options[0] = BIT_2 | BIT_1; in qla2x00_nvram_config()
5274 nv->firmware_options[0] = BIT_2 | BIT_1; in qla2x00_nvram_config()
5301 nv->host_p[1] = BIT_2; in qla2x00_nvram_config()
5322 nv->firmware_options[0] |= BIT_2; in qla2x00_nvram_config()
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Dqla_target.h482 #define CTIO7_FLAGS_DSD_PTR BIT_2
842 TRC_DO_WORK_ERR = BIT_2,
Dqla_inline.h388 RESOURCE_FORCE = BIT_2,
Dqla_gbl.h998 #define QLA2XX_INT_ERR BIT_2
Dqla_mbx.c801 (BIT_0 | BIT_1 | BIT_2); in qla2x00_execute_fw()
5753 mcp->mb[2] = BIT_2; in qla24xx_set_fcp_prio()
6344 if (subcode & BIT_2) { in qla83xx_access_control()
6352 if (!(subcode & (BIT_2 | BIT_5))) in qla83xx_access_control()
7017 if (options & BIT_2) { in ql26xx_led_config()
Dqla_attr.c1392 options |= BIT_3|BIT_2|BIT_1; in qla2x00_beacon_config_store()
1404 options |= BIT_2; in qla2x00_beacon_config_store()
Dqla_os.c6179 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) in qla24xx_process_purex_rdp()
/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic_ctx.c1348 arg1 &= ~(BIT_2 | BIT_3); in qlcnic_config_switch_port()
1354 arg2 |= (BIT_2 | BIT_3); in qlcnic_config_switch_port()
1364 arg2 &= ~(BIT_1 | BIT_2 | BIT_3); in qlcnic_config_switch_port()
1366 arg2 &= ~BIT_2; in qlcnic_config_switch_port()
1367 if (!(esw_cfg->offload_flags & BIT_2)) in qlcnic_config_switch_port()
1372 arg1 |= (BIT_2 | BIT_5); in qlcnic_config_switch_port()
Dqlcnic_hdr.h197 #define BIT_2 0x4 macro
494 #define TA_CTL_WRITE BIT_2
Dqlcnic.h921 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2
1316 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
Dqlcnic_83xx_hw.c748 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8); in qlcnic_83xx_enable_mbx_interrupt()
750 val = BIT_2; in qlcnic_83xx_enable_mbx_interrupt()
2022 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); in qlcnic_83xx_config_hw_lro()
3547 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16); in qlcnic_83xx_get_stats()
Dqlcnic_dcb.c551 if (mbx_out & BIT_2) in qlcnic_83xx_dcb_get_hw_capability()
Dqlcnic_hw.c1038 if (!(offload_flags & BIT_2)) in qlcnic_process_flags()
Dqlcnic_minidump.c25 #define QLCNIC_DUMP_ANDCRB BIT_2
Dqlcnic_83xx_init.c1023 #define QLC_83XX_MATCH_ENCAP_ID BIT_2
Dqlcnic_sriov_common.c384 if (status & BIT_2) in qlcnic_sriov_get_vf_vport_info()
Dqlcnic_io.c365 #define QLCNIC_ENCAP_INNER_L3_IP6 BIT_2
Dqlcnic_main.c1501 esw_cfg.offload_flags |= (BIT_1 | BIT_2); in qlcnic_set_default_offload_settings()
/drivers/scsi/qla4xxx/
Dql4_def.h82 #define BIT_2 0x4 macro
Dql4_os.c3558 conn->tcp_timer_scale |= BIT_2; in qla4xxx_copy_from_fwddb_param()
3685 SET_BITVAL(conn->tcp_timer_scale & BIT_2, options, BIT_3); in qla4xxx_copy_to_fwddb_param()
3686 SET_BITVAL(conn->tcp_timer_scale & BIT_1, options, BIT_2); in qla4xxx_copy_to_fwddb_param()
3794 conn->tcp_timer_scale |= BIT_2; in qla4xxx_copy_to_sess_conn_params()