| /drivers/dma/ |
| D | txx9dmac.h | 77 TXX9_DMA_REG32(CCR); /* Channel Control Register */
87 u32 CCR; member
278 desc->hwdesc.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
280 desc->hwdesc32.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
294 desc->hwdesc.CCR = ccr; in txx9dmac_desc_set_nosimple()
298 desc->hwdesc32.CCR = ccr; in txx9dmac_desc_set_nosimple()
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| D | txx9dmac.c | 295 channel64_readl(dc, CCR), in txx9dmac_dump_regs()
307 channel32_readl(dc, CCR), in txx9dmac_dump_regs()
313 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST); in txx9dmac_reset_chan()
326 channel_writel(dc, CCR, 0); in txx9dmac_reset_chan()
365 channel64_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
386 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
391 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
480 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
493 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
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| D | pl330.c | 340 CCR, enumerator
1270 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); in _dregs()
1276 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); in _dregs()
1425 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); in _setup_req()
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| /drivers/clocksource/ |
| D | timer-atmel-tcb.c | 104 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR)); in tc_clksrc_resume()
166 writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); in tc_shutdown()
215 ATMEL_TC_REG(2, CCR)); in tc_set_periodic()
225 tcaddr + ATMEL_TC_REG(2, CCR)); in tc_next_event()
325 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_dual_chan()
333 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); in tcb_setup_dual_chan()
349 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_single_chan()
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| /drivers/pwm/ |
| D | pwm-atmel-tcb.c | 166 ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_disable()
171 ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_disable()
253 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_enable()
520 ATMEL_TC_REG(channel, CCR)); in atmel_tcb_pwm_resume()
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| /drivers/dma/ti/ |
| D | omap-dma.c | 457 omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); in omap_dma_start()
469 val = omap_dma_chan_read(c, CCR); in omap_dma_drain_chan()
495 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
504 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
506 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
517 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
587 omap_dma_chan_write(c, CCR, d->ccr); in omap_dma_start_desc()
931 uint32_t ccr = omap_dma_chan_read(c, CCR); in omap_dma_tx_status()
1543 if (omap_dma_chan_read(c, CCR) & CCR_ENABLE) in omap_dma_busy()
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| /drivers/counter/ |
| D | microchip-tcb-capture.c | 130 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR), in mchp_tc_count_function_write()
137 ATMEL_TC_REG(priv->channel[1], CCR), in mchp_tc_count_function_write()
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| /drivers/tty/ |
| D | synclink_gt.c | 368 #define CCR 0x89 /* clock control */ macro
3814 wr_reg8(info, CCR, 0x49); in enable_loopback()
4097 wr_reg8(info, CCR, 0x69); in async_mode()
4310 wr_reg8(info, CCR, (unsigned char)val); in sync_mode()
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| /drivers/video/fbdev/ |
| D | imsttfb.c | 94 CCR = 0x00000008L,
|