1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 /*
4 * xHCI host controller driver
5 *
6 * Copyright (C) 2008 Intel Corp.
7 *
8 * Author: Sarah Sharp
9 * Some code borrowed from the Linux EHCI driver.
10 */
11
12 #ifndef __LINUX_XHCI_HCD_H
13 #define __LINUX_XHCI_HCD_H
14
15 #include <linux/usb.h>
16 #include <linux/timer.h>
17 #include <linux/kernel.h>
18 #include <linux/usb/hcd.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
20 #include <linux/io-64-nonatomic-hi-lo.h>
21 #include <linux/android_kabi.h>
22
23 /* Code sharing between pci-quirks and xhci hcd */
24 #include "xhci-ext-caps.h"
25 #include "pci-quirks.h"
26
27 /* max buffer size for trace and debug messages */
28 #define XHCI_MSG_MAX 500
29
30 /* xHCI PCI Configuration Registers */
31 #define XHCI_SBRN_OFFSET (0x60)
32
33 /* Max number of USB devices for any host controller - limit in section 6.1 */
34 #define MAX_HC_SLOTS 256
35 /* Section 5.3.3 - MaxPorts */
36 #define MAX_HC_PORTS 127
37
38 /*
39 * xHCI register interface.
40 * This corresponds to the eXtensible Host Controller Interface (xHCI)
41 * Revision 0.95 specification
42 */
43
44 /**
45 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
46 * @hc_capbase: length of the capabilities register and HC version number
47 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
48 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
49 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
50 * @hcc_params: HCCPARAMS - Capability Parameters
51 * @db_off: DBOFF - Doorbell array offset
52 * @run_regs_off: RTSOFF - Runtime register space offset
53 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
54 */
55 struct xhci_cap_regs {
56 __le32 hc_capbase;
57 __le32 hcs_params1;
58 __le32 hcs_params2;
59 __le32 hcs_params3;
60 __le32 hcc_params;
61 __le32 db_off;
62 __le32 run_regs_off;
63 __le32 hcc_params2; /* xhci 1.1 */
64 /* Reserved up to (CAPLENGTH - 0x1C) */
65 };
66
67 /* hc_capbase bitmasks */
68 /* bits 7:0 - how long is the Capabilities register */
69 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
70 /* bits 31:16 */
71 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
72
73 /* HCSPARAMS1 - hcs_params1 - bitmasks */
74 /* bits 0:7, Max Device Slots */
75 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
76 #define HCS_SLOTS_MASK 0xff
77 /* bits 8:18, Max Interrupters */
78 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
79 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
80 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
81
82 /* HCSPARAMS2 - hcs_params2 - bitmasks */
83 /* bits 0:3, frames or uframes that SW needs to queue transactions
84 * ahead of the HW to meet periodic deadlines */
85 #define HCS_IST(p) (((p) >> 0) & 0xf)
86 /* bits 4:7, max number of Event Ring segments */
87 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
88 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
89 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
90 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
91 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
92
93 /* HCSPARAMS3 - hcs_params3 - bitmasks */
94 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
95 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
96 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
97 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
98
99 /* HCCPARAMS - hcc_params - bitmasks */
100 /* true: HC can use 64-bit address pointers */
101 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
102 /* true: HC can do bandwidth negotiation */
103 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
104 /* true: HC uses 64-byte Device Context structures
105 * FIXME 64-byte context structures aren't supported yet.
106 */
107 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
108 /* true: HC has port power switches */
109 #define HCC_PPC(p) ((p) & (1 << 3))
110 /* true: HC has port indicators */
111 #define HCS_INDICATOR(p) ((p) & (1 << 4))
112 /* true: HC has Light HC Reset Capability */
113 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
114 /* true: HC supports latency tolerance messaging */
115 #define HCC_LTC(p) ((p) & (1 << 6))
116 /* true: no secondary Stream ID Support */
117 #define HCC_NSS(p) ((p) & (1 << 7))
118 /* true: HC supports Stopped - Short Packet */
119 #define HCC_SPC(p) ((p) & (1 << 9))
120 /* true: HC has Contiguous Frame ID Capability */
121 #define HCC_CFC(p) ((p) & (1 << 11))
122 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
123 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
124 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
125 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
126
127 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
128
129 /* db_off bitmask - bits 0:1 reserved */
130 #define DBOFF_MASK (~0x3)
131
132 /* run_regs_off bitmask - bits 0:4 reserved */
133 #define RTSOFF_MASK (~0x1f)
134
135 /* HCCPARAMS2 - hcc_params2 - bitmasks */
136 /* true: HC supports U3 entry Capability */
137 #define HCC2_U3C(p) ((p) & (1 << 0))
138 /* true: HC supports Configure endpoint command Max exit latency too large */
139 #define HCC2_CMC(p) ((p) & (1 << 1))
140 /* true: HC supports Force Save context Capability */
141 #define HCC2_FSC(p) ((p) & (1 << 2))
142 /* true: HC supports Compliance Transition Capability */
143 #define HCC2_CTC(p) ((p) & (1 << 3))
144 /* true: HC support Large ESIT payload Capability > 48k */
145 #define HCC2_LEC(p) ((p) & (1 << 4))
146 /* true: HC support Configuration Information Capability */
147 #define HCC2_CIC(p) ((p) & (1 << 5))
148 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
149 #define HCC2_ETC(p) ((p) & (1 << 6))
150
151 /* Number of registers per port */
152 #define NUM_PORT_REGS 4
153
154 #define PORTSC 0
155 #define PORTPMSC 1
156 #define PORTLI 2
157 #define PORTHLPMC 3
158
159 /**
160 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
161 * @command: USBCMD - xHC command register
162 * @status: USBSTS - xHC status register
163 * @page_size: This indicates the page size that the host controller
164 * supports. If bit n is set, the HC supports a page size
165 * of 2^(n+12), up to a 128MB page size.
166 * 4K is the minimum page size.
167 * @cmd_ring: CRP - 64-bit Command Ring Pointer
168 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
169 * @config_reg: CONFIG - Configure Register
170 * @port_status_base: PORTSCn - base address for Port Status and Control
171 * Each port has a Port Status and Control register,
172 * followed by a Port Power Management Status and Control
173 * register, a Port Link Info register, and a reserved
174 * register.
175 * @port_power_base: PORTPMSCn - base address for
176 * Port Power Management Status and Control
177 * @port_link_base: PORTLIn - base address for Port Link Info (current
178 * Link PM state and control) for USB 2.1 and USB 3.0
179 * devices.
180 */
181 struct xhci_op_regs {
182 __le32 command;
183 __le32 status;
184 __le32 page_size;
185 __le32 reserved1;
186 __le32 reserved2;
187 __le32 dev_notification;
188 __le64 cmd_ring;
189 /* rsvd: offset 0x20-2F */
190 __le32 reserved3[4];
191 __le64 dcbaa_ptr;
192 __le32 config_reg;
193 /* rsvd: offset 0x3C-3FF */
194 __le32 reserved4[241];
195 /* port 1 registers, which serve as a base address for other ports */
196 __le32 port_status_base;
197 __le32 port_power_base;
198 __le32 port_link_base;
199 __le32 reserved5;
200 /* registers for ports 2-255 */
201 __le32 reserved6[NUM_PORT_REGS*254];
202 };
203
204 /* USBCMD - USB command - command bitmasks */
205 /* start/stop HC execution - do not write unless HC is halted*/
206 #define CMD_RUN XHCI_CMD_RUN
207 /* Reset HC - resets internal HC state machine and all registers (except
208 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
209 * The xHCI driver must reinitialize the xHC after setting this bit.
210 */
211 #define CMD_RESET (1 << 1)
212 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
213 #define CMD_EIE XHCI_CMD_EIE
214 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
215 #define CMD_HSEIE XHCI_CMD_HSEIE
216 /* bits 4:6 are reserved (and should be preserved on writes). */
217 /* light reset (port status stays unchanged) - reset completed when this is 0 */
218 #define CMD_LRESET (1 << 7)
219 /* host controller save/restore state. */
220 #define CMD_CSS (1 << 8)
221 #define CMD_CRS (1 << 9)
222 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
223 #define CMD_EWE XHCI_CMD_EWE
224 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
225 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
226 * '0' means the xHC can power it off if all ports are in the disconnect,
227 * disabled, or powered-off state.
228 */
229 #define CMD_PM_INDEX (1 << 11)
230 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
231 #define CMD_ETE (1 << 14)
232 /* bits 15:31 are reserved (and should be preserved on writes). */
233
234 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
235 #define XHCI_RESET_SHORT_USEC (250 * 1000)
236
237 /* IMAN - Interrupt Management Register */
238 #define IMAN_IE (1 << 1)
239 #define IMAN_IP (1 << 0)
240
241 /* USBSTS - USB status - status bitmasks */
242 /* HC not running - set to 1 when run/stop bit is cleared. */
243 #define STS_HALT XHCI_STS_HALT
244 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
245 #define STS_FATAL (1 << 2)
246 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
247 #define STS_EINT (1 << 3)
248 /* port change detect */
249 #define STS_PORT (1 << 4)
250 /* bits 5:7 reserved and zeroed */
251 /* save state status - '1' means xHC is saving state */
252 #define STS_SAVE (1 << 8)
253 /* restore state status - '1' means xHC is restoring state */
254 #define STS_RESTORE (1 << 9)
255 /* true: save or restore error */
256 #define STS_SRE (1 << 10)
257 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
258 #define STS_CNR XHCI_STS_CNR
259 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
260 #define STS_HCE (1 << 12)
261 /* bits 13:31 reserved and should be preserved */
262
263 /*
264 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
265 * Generate a device notification event when the HC sees a transaction with a
266 * notification type that matches a bit set in this bit field.
267 */
268 #define DEV_NOTE_MASK (0xffff)
269 #define ENABLE_DEV_NOTE(x) (1 << (x))
270 /* Most of the device notification types should only be used for debug.
271 * SW does need to pay attention to function wake notifications.
272 */
273 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
274
275 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
276 /* bit 0 is the command ring cycle state */
277 /* stop ring operation after completion of the currently executing command */
278 #define CMD_RING_PAUSE (1 << 1)
279 /* stop ring immediately - abort the currently executing command */
280 #define CMD_RING_ABORT (1 << 2)
281 /* true: command ring is running */
282 #define CMD_RING_RUNNING (1 << 3)
283 /* bits 4:5 reserved and should be preserved */
284 /* Command Ring pointer - bit mask for the lower 32 bits. */
285 #define CMD_RING_RSVD_BITS (0x3f)
286
287 /* CONFIG - Configure Register - config_reg bitmasks */
288 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
289 #define MAX_DEVS(p) ((p) & 0xff)
290 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
291 #define CONFIG_U3E (1 << 8)
292 /* bit 9: Configuration Information Enable, xhci 1.1 */
293 #define CONFIG_CIE (1 << 9)
294 /* bits 10:31 - reserved and should be preserved */
295
296 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
297 /* true: device connected */
298 #define PORT_CONNECT (1 << 0)
299 /* true: port enabled */
300 #define PORT_PE (1 << 1)
301 /* bit 2 reserved and zeroed */
302 /* true: port has an over-current condition */
303 #define PORT_OC (1 << 3)
304 /* true: port reset signaling asserted */
305 #define PORT_RESET (1 << 4)
306 /* Port Link State - bits 5:8
307 * A read gives the current link PM state of the port,
308 * a write with Link State Write Strobe set sets the link state.
309 */
310 #define PORT_PLS_MASK (0xf << 5)
311 #define XDEV_U0 (0x0 << 5)
312 #define XDEV_U1 (0x1 << 5)
313 #define XDEV_U2 (0x2 << 5)
314 #define XDEV_U3 (0x3 << 5)
315 #define XDEV_DISABLED (0x4 << 5)
316 #define XDEV_RXDETECT (0x5 << 5)
317 #define XDEV_INACTIVE (0x6 << 5)
318 #define XDEV_POLLING (0x7 << 5)
319 #define XDEV_RECOVERY (0x8 << 5)
320 #define XDEV_HOT_RESET (0x9 << 5)
321 #define XDEV_COMP_MODE (0xa << 5)
322 #define XDEV_TEST_MODE (0xb << 5)
323 #define XDEV_RESUME (0xf << 5)
324
325 /* true: port has power (see HCC_PPC) */
326 #define PORT_POWER (1 << 9)
327 /* bits 10:13 indicate device speed:
328 * 0 - undefined speed - port hasn't be initialized by a reset yet
329 * 1 - full speed
330 * 2 - low speed
331 * 3 - high speed
332 * 4 - super speed
333 * 5-15 reserved
334 */
335 #define DEV_SPEED_MASK (0xf << 10)
336 #define XDEV_FS (0x1 << 10)
337 #define XDEV_LS (0x2 << 10)
338 #define XDEV_HS (0x3 << 10)
339 #define XDEV_SS (0x4 << 10)
340 #define XDEV_SSP (0x5 << 10)
341 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
342 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
343 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
344 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
345 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
346 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
347 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
348 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
349
350 /* Bits 20:23 in the Slot Context are the speed for the device */
351 #define SLOT_SPEED_FS (XDEV_FS << 10)
352 #define SLOT_SPEED_LS (XDEV_LS << 10)
353 #define SLOT_SPEED_HS (XDEV_HS << 10)
354 #define SLOT_SPEED_SS (XDEV_SS << 10)
355 #define SLOT_SPEED_SSP (XDEV_SSP << 10)
356 /* Port Indicator Control */
357 #define PORT_LED_OFF (0 << 14)
358 #define PORT_LED_AMBER (1 << 14)
359 #define PORT_LED_GREEN (2 << 14)
360 #define PORT_LED_MASK (3 << 14)
361 /* Port Link State Write Strobe - set this when changing link state */
362 #define PORT_LINK_STROBE (1 << 16)
363 /* true: connect status change */
364 #define PORT_CSC (1 << 17)
365 /* true: port enable change */
366 #define PORT_PEC (1 << 18)
367 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
368 * into an enabled state, and the device into the default state. A "warm" reset
369 * also resets the link, forcing the device through the link training sequence.
370 * SW can also look at the Port Reset register to see when warm reset is done.
371 */
372 #define PORT_WRC (1 << 19)
373 /* true: over-current change */
374 #define PORT_OCC (1 << 20)
375 /* true: reset change - 1 to 0 transition of PORT_RESET */
376 #define PORT_RC (1 << 21)
377 /* port link status change - set on some port link state transitions:
378 * Transition Reason
379 * ------------------------------------------------------------------------------
380 * - U3 to Resume Wakeup signaling from a device
381 * - Resume to Recovery to U0 USB 3.0 device resume
382 * - Resume to U0 USB 2.0 device resume
383 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
384 * - U3 to U0 Software resume of USB 2.0 device complete
385 * - U2 to U0 L1 resume of USB 2.1 device complete
386 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
387 * - U0 to disabled L1 entry error with USB 2.1 device
388 * - Any state to inactive Error on USB 3.0 port
389 */
390 #define PORT_PLC (1 << 22)
391 /* port configure error change - port failed to configure its link partner */
392 #define PORT_CEC (1 << 23)
393 #define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
394 PORT_RC | PORT_PLC | PORT_CEC)
395
396
397 /* Cold Attach Status - xHC can set this bit to report device attached during
398 * Sx state. Warm port reset should be perfomed to clear this bit and move port
399 * to connected state.
400 */
401 #define PORT_CAS (1 << 24)
402 /* wake on connect (enable) */
403 #define PORT_WKCONN_E (1 << 25)
404 /* wake on disconnect (enable) */
405 #define PORT_WKDISC_E (1 << 26)
406 /* wake on over-current (enable) */
407 #define PORT_WKOC_E (1 << 27)
408 /* bits 28:29 reserved */
409 /* true: device is non-removable - for USB 3.0 roothub emulation */
410 #define PORT_DEV_REMOVE (1 << 30)
411 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
412 #define PORT_WR (1 << 31)
413
414 /* We mark duplicate entries with -1 */
415 #define DUPLICATE_ENTRY ((u8)(-1))
416
417 /* Port Power Management Status and Control - port_power_base bitmasks */
418 /* Inactivity timer value for transitions into U1, in microseconds.
419 * Timeout can be up to 127us. 0xFF means an infinite timeout.
420 */
421 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
422 #define PORT_U1_TIMEOUT_MASK 0xff
423 /* Inactivity timer value for transitions into U2 */
424 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
425 #define PORT_U2_TIMEOUT_MASK (0xff << 8)
426 /* Bits 24:31 for port testing */
427
428 /* USB2 Protocol PORTSPMSC */
429 #define PORT_L1S_MASK 7
430 #define PORT_L1S_SUCCESS 1
431 #define PORT_RWE (1 << 3)
432 #define PORT_HIRD(p) (((p) & 0xf) << 4)
433 #define PORT_HIRD_MASK (0xf << 4)
434 #define PORT_L1DS_MASK (0xff << 8)
435 #define PORT_L1DS(p) (((p) & 0xff) << 8)
436 #define PORT_HLE (1 << 16)
437 #define PORT_TEST_MODE_SHIFT 28
438
439 /* USB3 Protocol PORTLI Port Link Information */
440 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
441 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
442
443 /* USB2 Protocol PORTHLPMC */
444 #define PORT_HIRDM(p)((p) & 3)
445 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
446 #define PORT_BESLD(p)(((p) & 0xf) << 10)
447
448 /* use 512 microseconds as USB2 LPM L1 default timeout. */
449 #define XHCI_L1_TIMEOUT 512
450
451 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
452 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
453 * by other operating systems.
454 *
455 * XHCI 1.0 errata 8/14/12 Table 13 notes:
456 * "Software should choose xHC BESL/BESLD field values that do not violate a
457 * device's resume latency requirements,
458 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
459 * or not program values < '4' if BLC = '0' and a BESL device is attached.
460 */
461 #define XHCI_DEFAULT_BESL 4
462
463 /*
464 * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
465 * to complete link training. usually link trainig completes much faster
466 * so check status 10 times with 36ms sleep in places we need to wait for
467 * polling to complete.
468 */
469 #define XHCI_PORT_POLLING_LFPS_TIME 36
470
471 /**
472 * struct xhci_intr_reg - Interrupt Register Set
473 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
474 * interrupts and check for pending interrupts.
475 * @irq_control: IMOD - Interrupt Moderation Register.
476 * Used to throttle interrupts.
477 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
478 * @erst_base: ERST base address.
479 * @erst_dequeue: Event ring dequeue pointer.
480 *
481 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
482 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
483 * multiple segments of the same size. The HC places events on the ring and
484 * "updates the Cycle bit in the TRBs to indicate to software the current
485 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
486 * updates the dequeue pointer.
487 */
488 struct xhci_intr_reg {
489 __le32 irq_pending;
490 __le32 irq_control;
491 __le32 erst_size;
492 __le32 rsvd;
493 __le64 erst_base;
494 __le64 erst_dequeue;
495 };
496
497 /* irq_pending bitmasks */
498 #define ER_IRQ_PENDING(p) ((p) & 0x1)
499 /* bits 2:31 need to be preserved */
500 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
501 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
502 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
503 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
504
505 /* irq_control bitmasks */
506 /* Minimum interval between interrupts (in 250ns intervals). The interval
507 * between interrupts will be longer if there are no events on the event ring.
508 * Default is 4000 (1 ms).
509 */
510 #define ER_IRQ_INTERVAL_MASK (0xffff)
511 /* Counter used to count down the time to the next interrupt - HW use only */
512 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
513
514 /* erst_size bitmasks */
515 /* Preserve bits 16:31 of erst_size */
516 #define ERST_SIZE_MASK (0xffff << 16)
517
518 /* erst_base bitmasks */
519 #define ERST_BASE_RSVDP (GENMASK_ULL(5, 0))
520
521 /* erst_dequeue bitmasks */
522 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
523 * where the current dequeue pointer lies. This is an optional HW hint.
524 */
525 #define ERST_DESI_MASK (0x7)
526 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
527 * a work queue (or delayed service routine)?
528 */
529 #define ERST_EHB (1 << 3)
530 #define ERST_PTR_MASK (GENMASK_ULL(63, 4))
531
532 /**
533 * struct xhci_run_regs
534 * @microframe_index:
535 * MFINDEX - current microframe number
536 *
537 * Section 5.5 Host Controller Runtime Registers:
538 * "Software should read and write these registers using only Dword (32 bit)
539 * or larger accesses"
540 */
541 struct xhci_run_regs {
542 __le32 microframe_index;
543 __le32 rsvd[7];
544 struct xhci_intr_reg ir_set[128];
545 };
546
547 /**
548 * struct doorbell_array
549 *
550 * Bits 0 - 7: Endpoint target
551 * Bits 8 - 15: RsvdZ
552 * Bits 16 - 31: Stream ID
553 *
554 * Section 5.6
555 */
556 struct xhci_doorbell_array {
557 __le32 doorbell[256];
558 };
559
560 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
561 #define DB_VALUE_HOST 0x00000000
562
563 /**
564 * struct xhci_protocol_caps
565 * @revision: major revision, minor revision, capability ID,
566 * and next capability pointer.
567 * @name_string: Four ASCII characters to say which spec this xHC
568 * follows, typically "USB ".
569 * @port_info: Port offset, count, and protocol-defined information.
570 */
571 struct xhci_protocol_caps {
572 u32 revision;
573 u32 name_string;
574 u32 port_info;
575 };
576
577 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
578 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
579 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
580 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
581 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
582
583 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
584 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
585 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
586 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
587 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
588 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
589
590 #define PLT_MASK (0x03 << 6)
591 #define PLT_SYM (0x00 << 6)
592 #define PLT_ASYM_RX (0x02 << 6)
593 #define PLT_ASYM_TX (0x03 << 6)
594
595 /**
596 * struct xhci_container_ctx
597 * @type: Type of context. Used to calculated offsets to contained contexts.
598 * @size: Size of the context data
599 * @bytes: The raw context data given to HW
600 * @dma: dma address of the bytes
601 *
602 * Represents either a Device or Input context. Holds a pointer to the raw
603 * memory used for the context (bytes) and dma address of it (dma).
604 */
605 struct xhci_container_ctx {
606 unsigned type;
607 #define XHCI_CTX_TYPE_DEVICE 0x1
608 #define XHCI_CTX_TYPE_INPUT 0x2
609
610 int size;
611
612 u8 *bytes;
613 dma_addr_t dma;
614 };
615
616 /**
617 * struct xhci_slot_ctx
618 * @dev_info: Route string, device speed, hub info, and last valid endpoint
619 * @dev_info2: Max exit latency for device number, root hub port number
620 * @tt_info: tt_info is used to construct split transaction tokens
621 * @dev_state: slot state and device address
622 *
623 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
624 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
625 * reserved at the end of the slot context for HC internal use.
626 */
627 struct xhci_slot_ctx {
628 __le32 dev_info;
629 __le32 dev_info2;
630 __le32 tt_info;
631 __le32 dev_state;
632 /* offset 0x10 to 0x1f reserved for HC internal use */
633 __le32 reserved[4];
634 };
635
636 /* dev_info bitmasks */
637 /* Route String - 0:19 */
638 #define ROUTE_STRING_MASK (0xfffff)
639 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
640 #define DEV_SPEED (0xf << 20)
641 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
642 /* bit 24 reserved */
643 /* Is this LS/FS device connected through a HS hub? - bit 25 */
644 #define DEV_MTT (0x1 << 25)
645 /* Set if the device is a hub - bit 26 */
646 #define DEV_HUB (0x1 << 26)
647 /* Index of the last valid endpoint context in this device context - 27:31 */
648 #define LAST_CTX_MASK (0x1f << 27)
649 #define LAST_CTX(p) ((p) << 27)
650 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
651 #define SLOT_FLAG (1 << 0)
652 #define EP0_FLAG (1 << 1)
653
654 /* dev_info2 bitmasks */
655 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
656 #define MAX_EXIT (0xffff)
657 /* Root hub port number that is needed to access the USB device */
658 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
659 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
660 /* Maximum number of ports under a hub device */
661 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
662 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
663
664 /* tt_info bitmasks */
665 /*
666 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
667 * The Slot ID of the hub that isolates the high speed signaling from
668 * this low or full-speed device. '0' if attached to root hub port.
669 */
670 #define TT_SLOT (0xff)
671 /*
672 * The number of the downstream facing port of the high-speed hub
673 * '0' if the device is not low or full speed.
674 */
675 #define TT_PORT (0xff << 8)
676 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
677 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
678
679 /* dev_state bitmasks */
680 /* USB device address - assigned by the HC */
681 #define DEV_ADDR_MASK (0xff)
682 /* bits 8:26 reserved */
683 /* Slot state */
684 #define SLOT_STATE (0x1f << 27)
685 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
686
687 #define SLOT_STATE_DISABLED 0
688 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
689 #define SLOT_STATE_DEFAULT 1
690 #define SLOT_STATE_ADDRESSED 2
691 #define SLOT_STATE_CONFIGURED 3
692
693 /**
694 * struct xhci_ep_ctx
695 * @ep_info: endpoint state, streams, mult, and interval information.
696 * @ep_info2: information on endpoint type, max packet size, max burst size,
697 * error count, and whether the HC will force an event for all
698 * transactions.
699 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
700 * defines one stream, this points to the endpoint transfer ring.
701 * Otherwise, it points to a stream context array, which has a
702 * ring pointer for each flow.
703 * @tx_info:
704 * Average TRB lengths for the endpoint ring and
705 * max payload within an Endpoint Service Interval Time (ESIT).
706 *
707 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
708 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
709 * reserved at the end of the endpoint context for HC internal use.
710 */
711 struct xhci_ep_ctx {
712 __le32 ep_info;
713 __le32 ep_info2;
714 __le64 deq;
715 __le32 tx_info;
716 /* offset 0x14 - 0x1f reserved for HC internal use */
717 __le32 reserved[3];
718 };
719
720 /* ep_info bitmasks */
721 /*
722 * Endpoint State - bits 0:2
723 * 0 - disabled
724 * 1 - running
725 * 2 - halted due to halt condition - ok to manipulate endpoint ring
726 * 3 - stopped
727 * 4 - TRB error
728 * 5-7 - reserved
729 */
730 #define EP_STATE_MASK (0x7)
731 #define EP_STATE_DISABLED 0
732 #define EP_STATE_RUNNING 1
733 #define EP_STATE_HALTED 2
734 #define EP_STATE_STOPPED 3
735 #define EP_STATE_ERROR 4
736 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
737
738 /* Mult - Max number of burtst within an interval, in EP companion desc. */
739 #define EP_MULT(p) (((p) & 0x3) << 8)
740 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
741 /* bits 10:14 are Max Primary Streams */
742 /* bit 15 is Linear Stream Array */
743 /* Interval - period between requests to an endpoint - 125u increments. */
744 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
745 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
746 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
747 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
748 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
749 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
750 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
751 #define EP_HAS_LSA (1 << 15)
752 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
753 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
754
755 /* ep_info2 bitmasks */
756 /*
757 * Force Event - generate transfer events for all TRBs for this endpoint
758 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
759 */
760 #define FORCE_EVENT (0x1)
761 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
762 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
763 #define EP_TYPE(p) ((p) << 3)
764 #define ISOC_OUT_EP 1
765 #define BULK_OUT_EP 2
766 #define INT_OUT_EP 3
767 #define CTRL_EP 4
768 #define ISOC_IN_EP 5
769 #define BULK_IN_EP 6
770 #define INT_IN_EP 7
771 /* bit 6 reserved */
772 /* bit 7 is Host Initiate Disable - for disabling stream selection */
773 #define MAX_BURST(p) (((p)&0xff) << 8)
774 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
775 #define MAX_PACKET(p) (((p)&0xffff) << 16)
776 #define MAX_PACKET_MASK (0xffff << 16)
777 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
778
779 /* tx_info bitmasks */
780 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
781 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
782 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
783 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
784
785 /* deq bitmasks */
786 #define EP_CTX_CYCLE_MASK (1 << 0)
787 #define SCTX_DEQ_MASK (~0xfL)
788
789
790 /**
791 * struct xhci_input_control_context
792 * Input control context; see section 6.2.5.
793 *
794 * @drop_context: set the bit of the endpoint context you want to disable
795 * @add_context: set the bit of the endpoint context you want to enable
796 */
797 struct xhci_input_control_ctx {
798 __le32 drop_flags;
799 __le32 add_flags;
800 __le32 rsvd2[6];
801 };
802
803 #define EP_IS_ADDED(ctrl_ctx, i) \
804 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
805 #define EP_IS_DROPPED(ctrl_ctx, i) \
806 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
807
808 /* Represents everything that is needed to issue a command on the command ring.
809 * It's useful to pre-allocate these for commands that cannot fail due to
810 * out-of-memory errors, like freeing streams.
811 */
812 struct xhci_command {
813 /* Input context for changing device state */
814 struct xhci_container_ctx *in_ctx;
815 u32 status;
816 int slot_id;
817 /* If completion is null, no one is waiting on this command
818 * and the structure can be freed after the command completes.
819 */
820 struct completion *completion;
821 union xhci_trb *command_trb;
822 struct list_head cmd_list;
823
824 /* xHCI command response timeout in milliseconds */
825 unsigned int timeout_ms;
826
827 ANDROID_KABI_RESERVE(1);
828 ANDROID_KABI_RESERVE(2);
829 };
830
831 /* drop context bitmasks */
832 #define DROP_EP(x) (0x1 << x)
833 /* add context bitmasks */
834 #define ADD_EP(x) (0x1 << x)
835
836 struct xhci_stream_ctx {
837 /* 64-bit stream ring address, cycle state, and stream type */
838 __le64 stream_ring;
839 /* offset 0x14 - 0x1f reserved for HC internal use */
840 __le32 reserved[2];
841 };
842
843 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
844 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
845 /* Secondary stream array type, dequeue pointer is to a transfer ring */
846 #define SCT_SEC_TR 0
847 /* Primary stream array type, dequeue pointer is to a transfer ring */
848 #define SCT_PRI_TR 1
849 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
850 #define SCT_SSA_8 2
851 #define SCT_SSA_16 3
852 #define SCT_SSA_32 4
853 #define SCT_SSA_64 5
854 #define SCT_SSA_128 6
855 #define SCT_SSA_256 7
856
857 /* Assume no secondary streams for now */
858 struct xhci_stream_info {
859 struct xhci_ring **stream_rings;
860 /* Number of streams, including stream 0 (which drivers can't use) */
861 unsigned int num_streams;
862 /* The stream context array may be bigger than
863 * the number of streams the driver asked for
864 */
865 struct xhci_stream_ctx *stream_ctx_array;
866 unsigned int num_stream_ctxs;
867 dma_addr_t ctx_array_dma;
868 /* For mapping physical TRB addresses to segments in stream rings */
869 struct radix_tree_root trb_address_map;
870 struct xhci_command *free_streams_command;
871 };
872
873 #define SMALL_STREAM_ARRAY_SIZE 256
874 #define MEDIUM_STREAM_ARRAY_SIZE 1024
875
876 /* Some Intel xHCI host controllers need software to keep track of the bus
877 * bandwidth. Keep track of endpoint info here. Each root port is allocated
878 * the full bus bandwidth. We must also treat TTs (including each port under a
879 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
880 * (DMI) also limits the total bandwidth (across all domains) that can be used.
881 */
882 struct xhci_bw_info {
883 /* ep_interval is zero-based */
884 unsigned int ep_interval;
885 /* mult and num_packets are one-based */
886 unsigned int mult;
887 unsigned int num_packets;
888 unsigned int max_packet_size;
889 unsigned int max_esit_payload;
890 unsigned int type;
891 };
892
893 /* "Block" sizes in bytes the hardware uses for different device speeds.
894 * The logic in this part of the hardware limits the number of bits the hardware
895 * can use, so must represent bandwidth in a less precise manner to mimic what
896 * the scheduler hardware computes.
897 */
898 #define FS_BLOCK 1
899 #define HS_BLOCK 4
900 #define SS_BLOCK 16
901 #define DMI_BLOCK 32
902
903 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
904 * with each byte transferred. SuperSpeed devices have an initial overhead to
905 * set up bursts. These are in blocks, see above. LS overhead has already been
906 * translated into FS blocks.
907 */
908 #define DMI_OVERHEAD 8
909 #define DMI_OVERHEAD_BURST 4
910 #define SS_OVERHEAD 8
911 #define SS_OVERHEAD_BURST 32
912 #define HS_OVERHEAD 26
913 #define FS_OVERHEAD 20
914 #define LS_OVERHEAD 128
915 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
916 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
917 * of overhead associated with split transfers crossing microframe boundaries.
918 * 31 blocks is pure protocol overhead.
919 */
920 #define TT_HS_OVERHEAD (31 + 94)
921 #define TT_DMI_OVERHEAD (25 + 12)
922
923 /* Bandwidth limits in blocks */
924 #define FS_BW_LIMIT 1285
925 #define TT_BW_LIMIT 1320
926 #define HS_BW_LIMIT 1607
927 #define SS_BW_LIMIT_IN 3906
928 #define DMI_BW_LIMIT_IN 3906
929 #define SS_BW_LIMIT_OUT 3906
930 #define DMI_BW_LIMIT_OUT 3906
931
932 /* Percentage of bus bandwidth reserved for non-periodic transfers */
933 #define FS_BW_RESERVED 10
934 #define HS_BW_RESERVED 20
935 #define SS_BW_RESERVED 10
936
937 struct xhci_virt_ep {
938 struct xhci_virt_device *vdev; /* parent */
939 unsigned int ep_index;
940 struct xhci_ring *ring;
941 /* Related to endpoints that are configured to use stream IDs only */
942 struct xhci_stream_info *stream_info;
943 /* Temporary storage in case the configure endpoint command fails and we
944 * have to restore the device state to the previous state
945 */
946 struct xhci_ring *new_ring;
947 unsigned int err_count;
948 unsigned int ep_state;
949 #define SET_DEQ_PENDING (1 << 0)
950 #define EP_HALTED (1 << 1) /* For stall handling */
951 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
952 /* Transitioning the endpoint to using streams, don't enqueue URBs */
953 #define EP_GETTING_STREAMS (1 << 3)
954 #define EP_HAS_STREAMS (1 << 4)
955 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
956 #define EP_GETTING_NO_STREAMS (1 << 5)
957 #define EP_HARD_CLEAR_TOGGLE (1 << 6)
958 #define EP_SOFT_CLEAR_TOGGLE (1 << 7)
959 /* usb_hub_clear_tt_buffer is in progress */
960 #define EP_CLEARING_TT (1 << 8)
961 /* ---- Related to URB cancellation ---- */
962 struct list_head cancelled_td_list;
963 struct xhci_hcd *xhci;
964 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
965 * command. We'll need to update the ring's dequeue segment and dequeue
966 * pointer after the command completes.
967 */
968 struct xhci_segment *queued_deq_seg;
969 union xhci_trb *queued_deq_ptr;
970 /*
971 * Sometimes the xHC can not process isochronous endpoint ring quickly
972 * enough, and it will miss some isoc tds on the ring and generate
973 * a Missed Service Error Event.
974 * Set skip flag when receive a Missed Service Error Event and
975 * process the missed tds on the endpoint ring.
976 */
977 bool skip;
978 /* Bandwidth checking storage */
979 struct xhci_bw_info bw_info;
980 struct list_head bw_endpoint_list;
981 /* Isoch Frame ID checking storage */
982 int next_frame_id;
983 /* Use new Isoch TRB layout needed for extended TBC support */
984 bool use_extended_tbc;
985 /* set if this endpoint is controlled via sideband access*/
986 struct xhci_sideband *sideband;
987 };
988
989 enum xhci_overhead_type {
990 LS_OVERHEAD_TYPE = 0,
991 FS_OVERHEAD_TYPE,
992 HS_OVERHEAD_TYPE,
993 };
994
995 struct xhci_interval_bw {
996 unsigned int num_packets;
997 /* Sorted by max packet size.
998 * Head of the list is the greatest max packet size.
999 */
1000 struct list_head endpoints;
1001 /* How many endpoints of each speed are present. */
1002 unsigned int overhead[3];
1003 };
1004
1005 #define XHCI_MAX_INTERVAL 16
1006
1007 struct xhci_interval_bw_table {
1008 unsigned int interval0_esit_payload;
1009 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
1010 /* Includes reserved bandwidth for async endpoints */
1011 unsigned int bw_used;
1012 unsigned int ss_bw_in;
1013 unsigned int ss_bw_out;
1014 };
1015
1016 #define EP_CTX_PER_DEV 31
1017
1018 struct xhci_virt_device {
1019 int slot_id;
1020 struct usb_device *udev;
1021 /*
1022 * Commands to the hardware are passed an "input context" that
1023 * tells the hardware what to change in its data structures.
1024 * The hardware will return changes in an "output context" that
1025 * software must allocate for the hardware. We need to keep
1026 * track of input and output contexts separately because
1027 * these commands might fail and we don't trust the hardware.
1028 */
1029 struct xhci_container_ctx *out_ctx;
1030 /* Used for addressing devices and configuration changes */
1031 struct xhci_container_ctx *in_ctx;
1032 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
1033 u8 fake_port;
1034 u8 real_port;
1035 struct xhci_interval_bw_table *bw_table;
1036 struct xhci_tt_bw_info *tt_info;
1037 /*
1038 * flags for state tracking based on events and issued commands.
1039 * Software can not rely on states from output contexts because of
1040 * latency between events and xHC updating output context values.
1041 * See xhci 1.1 section 4.8.3 for more details
1042 */
1043 unsigned long flags;
1044 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
1045
1046 /* The current max exit latency for the enabled USB3 link states. */
1047 u16 current_mel;
1048 /* Used for the debugfs interfaces. */
1049 void *debugfs_private;
1050 /* set if this device is registered for sideband access */
1051 struct xhci_sideband *sideband;
1052 };
1053
1054 /*
1055 * For each roothub, keep track of the bandwidth information for each periodic
1056 * interval.
1057 *
1058 * If a high speed hub is attached to the roothub, each TT associated with that
1059 * hub is a separate bandwidth domain. The interval information for the
1060 * endpoints on the devices under that TT will appear in the TT structure.
1061 */
1062 struct xhci_root_port_bw_info {
1063 struct list_head tts;
1064 unsigned int num_active_tts;
1065 struct xhci_interval_bw_table bw_table;
1066 };
1067
1068 struct xhci_tt_bw_info {
1069 struct list_head tt_list;
1070 int slot_id;
1071 int ttport;
1072 struct xhci_interval_bw_table bw_table;
1073 int active_eps;
1074 };
1075
1076
1077 /**
1078 * struct xhci_device_context_array
1079 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1080 */
1081 struct xhci_device_context_array {
1082 /* 64-bit device addresses; we only write 32-bit addresses */
1083 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1084 /* private xHCD pointers */
1085 dma_addr_t dma;
1086 };
1087 /* TODO: write function to set the 64-bit device DMA address */
1088 /*
1089 * TODO: change this to be dynamically sized at HC mem init time since the HC
1090 * might not be able to handle the maximum number of devices possible.
1091 */
1092
1093
1094 struct xhci_transfer_event {
1095 /* 64-bit buffer address, or immediate data */
1096 __le64 buffer;
1097 __le32 transfer_len;
1098 /* This field is interpreted differently based on the type of TRB */
1099 __le32 flags;
1100 };
1101
1102 /* Transfer event TRB length bit mask */
1103 /* bits 0:23 */
1104 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1105
1106 /** Transfer Event bit fields **/
1107 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1108
1109 /* Completion Code - only applicable for some types of TRBs */
1110 #define COMP_CODE_MASK (0xff << 24)
1111 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1112 #define COMP_INVALID 0
1113 #define COMP_SUCCESS 1
1114 #define COMP_DATA_BUFFER_ERROR 2
1115 #define COMP_BABBLE_DETECTED_ERROR 3
1116 #define COMP_USB_TRANSACTION_ERROR 4
1117 #define COMP_TRB_ERROR 5
1118 #define COMP_STALL_ERROR 6
1119 #define COMP_RESOURCE_ERROR 7
1120 #define COMP_BANDWIDTH_ERROR 8
1121 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1122 #define COMP_INVALID_STREAM_TYPE_ERROR 10
1123 #define COMP_SLOT_NOT_ENABLED_ERROR 11
1124 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1125 #define COMP_SHORT_PACKET 13
1126 #define COMP_RING_UNDERRUN 14
1127 #define COMP_RING_OVERRUN 15
1128 #define COMP_VF_EVENT_RING_FULL_ERROR 16
1129 #define COMP_PARAMETER_ERROR 17
1130 #define COMP_BANDWIDTH_OVERRUN_ERROR 18
1131 #define COMP_CONTEXT_STATE_ERROR 19
1132 #define COMP_NO_PING_RESPONSE_ERROR 20
1133 #define COMP_EVENT_RING_FULL_ERROR 21
1134 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1135 #define COMP_MISSED_SERVICE_ERROR 23
1136 #define COMP_COMMAND_RING_STOPPED 24
1137 #define COMP_COMMAND_ABORTED 25
1138 #define COMP_STOPPED 26
1139 #define COMP_STOPPED_LENGTH_INVALID 27
1140 #define COMP_STOPPED_SHORT_PACKET 28
1141 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1142 #define COMP_ISOCH_BUFFER_OVERRUN 31
1143 #define COMP_EVENT_LOST_ERROR 32
1144 #define COMP_UNDEFINED_ERROR 33
1145 #define COMP_INVALID_STREAM_ID_ERROR 34
1146 #define COMP_SECONDARY_BANDWIDTH_ERROR 35
1147 #define COMP_SPLIT_TRANSACTION_ERROR 36
1148
xhci_trb_comp_code_string(u8 status)1149 static inline const char *xhci_trb_comp_code_string(u8 status)
1150 {
1151 switch (status) {
1152 case COMP_INVALID:
1153 return "Invalid";
1154 case COMP_SUCCESS:
1155 return "Success";
1156 case COMP_DATA_BUFFER_ERROR:
1157 return "Data Buffer Error";
1158 case COMP_BABBLE_DETECTED_ERROR:
1159 return "Babble Detected";
1160 case COMP_USB_TRANSACTION_ERROR:
1161 return "USB Transaction Error";
1162 case COMP_TRB_ERROR:
1163 return "TRB Error";
1164 case COMP_STALL_ERROR:
1165 return "Stall Error";
1166 case COMP_RESOURCE_ERROR:
1167 return "Resource Error";
1168 case COMP_BANDWIDTH_ERROR:
1169 return "Bandwidth Error";
1170 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1171 return "No Slots Available Error";
1172 case COMP_INVALID_STREAM_TYPE_ERROR:
1173 return "Invalid Stream Type Error";
1174 case COMP_SLOT_NOT_ENABLED_ERROR:
1175 return "Slot Not Enabled Error";
1176 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1177 return "Endpoint Not Enabled Error";
1178 case COMP_SHORT_PACKET:
1179 return "Short Packet";
1180 case COMP_RING_UNDERRUN:
1181 return "Ring Underrun";
1182 case COMP_RING_OVERRUN:
1183 return "Ring Overrun";
1184 case COMP_VF_EVENT_RING_FULL_ERROR:
1185 return "VF Event Ring Full Error";
1186 case COMP_PARAMETER_ERROR:
1187 return "Parameter Error";
1188 case COMP_BANDWIDTH_OVERRUN_ERROR:
1189 return "Bandwidth Overrun Error";
1190 case COMP_CONTEXT_STATE_ERROR:
1191 return "Context State Error";
1192 case COMP_NO_PING_RESPONSE_ERROR:
1193 return "No Ping Response Error";
1194 case COMP_EVENT_RING_FULL_ERROR:
1195 return "Event Ring Full Error";
1196 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1197 return "Incompatible Device Error";
1198 case COMP_MISSED_SERVICE_ERROR:
1199 return "Missed Service Error";
1200 case COMP_COMMAND_RING_STOPPED:
1201 return "Command Ring Stopped";
1202 case COMP_COMMAND_ABORTED:
1203 return "Command Aborted";
1204 case COMP_STOPPED:
1205 return "Stopped";
1206 case COMP_STOPPED_LENGTH_INVALID:
1207 return "Stopped - Length Invalid";
1208 case COMP_STOPPED_SHORT_PACKET:
1209 return "Stopped - Short Packet";
1210 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1211 return "Max Exit Latency Too Large Error";
1212 case COMP_ISOCH_BUFFER_OVERRUN:
1213 return "Isoch Buffer Overrun";
1214 case COMP_EVENT_LOST_ERROR:
1215 return "Event Lost Error";
1216 case COMP_UNDEFINED_ERROR:
1217 return "Undefined Error";
1218 case COMP_INVALID_STREAM_ID_ERROR:
1219 return "Invalid Stream ID Error";
1220 case COMP_SECONDARY_BANDWIDTH_ERROR:
1221 return "Secondary Bandwidth Error";
1222 case COMP_SPLIT_TRANSACTION_ERROR:
1223 return "Split Transaction Error";
1224 default:
1225 return "Unknown!!";
1226 }
1227 }
1228
1229 struct xhci_link_trb {
1230 /* 64-bit segment pointer*/
1231 __le64 segment_ptr;
1232 __le32 intr_target;
1233 __le32 control;
1234 };
1235
1236 /* control bitfields */
1237 #define LINK_TOGGLE (0x1<<1)
1238
1239 /* Command completion event TRB */
1240 struct xhci_event_cmd {
1241 /* Pointer to command TRB, or the value passed by the event data trb */
1242 __le64 cmd_trb;
1243 __le32 status;
1244 __le32 flags;
1245 };
1246
1247 /* flags bitmasks */
1248
1249 /* Address device - disable SetAddress */
1250 #define TRB_BSR (1<<9)
1251
1252 /* Configure Endpoint - Deconfigure */
1253 #define TRB_DC (1<<9)
1254
1255 /* Stop Ring - Transfer State Preserve */
1256 #define TRB_TSP (1<<9)
1257
1258 enum xhci_ep_reset_type {
1259 EP_HARD_RESET,
1260 EP_SOFT_RESET,
1261 };
1262
1263 /* Force Event */
1264 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1265 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1266
1267 /* Set Latency Tolerance Value */
1268 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1269
1270 /* Get Port Bandwidth */
1271 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1272
1273 /* Force Header */
1274 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1275 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1276
1277 enum xhci_setup_dev {
1278 SETUP_CONTEXT_ONLY,
1279 SETUP_CONTEXT_ADDRESS,
1280 };
1281
1282 /* bits 16:23 are the virtual function ID */
1283 /* bits 24:31 are the slot ID */
1284 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1285 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1286
1287 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1288 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1289 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1290
1291 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1292 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1293 #define LAST_EP_INDEX 30
1294
1295 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1296 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1297 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1298 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1299
1300 /* Link TRB specific fields */
1301 #define TRB_TC (1<<1)
1302
1303 /* Port Status Change Event TRB fields */
1304 /* Port ID - bits 31:24 */
1305 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1306
1307 #define EVENT_DATA (1 << 2)
1308
1309 /* Normal TRB fields */
1310 /* transfer_len bitmasks - bits 0:16 */
1311 #define TRB_LEN(p) ((p) & 0x1ffff)
1312 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1313 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1314 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1315 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1316 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1317 /* Interrupter Target - which MSI-X vector to target the completion event at */
1318 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1319 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1320 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1321 #define TRB_TBC(p) (((p) & 0x3) << 7)
1322 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1323
1324 /* Cycle bit - indicates TRB ownership by HC or HCD */
1325 #define TRB_CYCLE (1<<0)
1326 /*
1327 * Force next event data TRB to be evaluated before task switch.
1328 * Used to pass OS data back after a TD completes.
1329 */
1330 #define TRB_ENT (1<<1)
1331 /* Interrupt on short packet */
1332 #define TRB_ISP (1<<2)
1333 /* Set PCIe no snoop attribute */
1334 #define TRB_NO_SNOOP (1<<3)
1335 /* Chain multiple TRBs into a TD */
1336 #define TRB_CHAIN (1<<4)
1337 /* Interrupt on completion */
1338 #define TRB_IOC (1<<5)
1339 /* The buffer pointer contains immediate data */
1340 #define TRB_IDT (1<<6)
1341 /* TDs smaller than this might use IDT */
1342 #define TRB_IDT_MAX_SIZE 8
1343
1344 /* Block Event Interrupt */
1345 #define TRB_BEI (1<<9)
1346
1347 /* Control transfer TRB specific fields */
1348 #define TRB_DIR_IN (1<<16)
1349 #define TRB_TX_TYPE(p) ((p) << 16)
1350 #define TRB_DATA_OUT 2
1351 #define TRB_DATA_IN 3
1352
1353 /* Isochronous TRB specific fields */
1354 #define TRB_SIA (1<<31)
1355 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1356
1357 /* TRB cache size for xHC with TRB cache */
1358 #define TRB_CACHE_SIZE_HS 8
1359 #define TRB_CACHE_SIZE_SS 16
1360
1361 struct xhci_generic_trb {
1362 __le32 field[4];
1363 };
1364
1365 union xhci_trb {
1366 struct xhci_link_trb link;
1367 struct xhci_transfer_event trans_event;
1368 struct xhci_event_cmd event_cmd;
1369 struct xhci_generic_trb generic;
1370 };
1371
1372 /* TRB bit mask */
1373 #define TRB_TYPE_BITMASK (0xfc00)
1374 #define TRB_TYPE(p) ((p) << 10)
1375 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1376 /* TRB type IDs */
1377 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1378 #define TRB_NORMAL 1
1379 /* setup stage for control transfers */
1380 #define TRB_SETUP 2
1381 /* data stage for control transfers */
1382 #define TRB_DATA 3
1383 /* status stage for control transfers */
1384 #define TRB_STATUS 4
1385 /* isoc transfers */
1386 #define TRB_ISOC 5
1387 /* TRB for linking ring segments */
1388 #define TRB_LINK 6
1389 #define TRB_EVENT_DATA 7
1390 /* Transfer Ring No-op (not for the command ring) */
1391 #define TRB_TR_NOOP 8
1392 /* Command TRBs */
1393 /* Enable Slot Command */
1394 #define TRB_ENABLE_SLOT 9
1395 /* Disable Slot Command */
1396 #define TRB_DISABLE_SLOT 10
1397 /* Address Device Command */
1398 #define TRB_ADDR_DEV 11
1399 /* Configure Endpoint Command */
1400 #define TRB_CONFIG_EP 12
1401 /* Evaluate Context Command */
1402 #define TRB_EVAL_CONTEXT 13
1403 /* Reset Endpoint Command */
1404 #define TRB_RESET_EP 14
1405 /* Stop Transfer Ring Command */
1406 #define TRB_STOP_RING 15
1407 /* Set Transfer Ring Dequeue Pointer Command */
1408 #define TRB_SET_DEQ 16
1409 /* Reset Device Command */
1410 #define TRB_RESET_DEV 17
1411 /* Force Event Command (opt) */
1412 #define TRB_FORCE_EVENT 18
1413 /* Negotiate Bandwidth Command (opt) */
1414 #define TRB_NEG_BANDWIDTH 19
1415 /* Set Latency Tolerance Value Command (opt) */
1416 #define TRB_SET_LT 20
1417 /* Get port bandwidth Command */
1418 #define TRB_GET_BW 21
1419 /* Force Header Command - generate a transaction or link management packet */
1420 #define TRB_FORCE_HEADER 22
1421 /* No-op Command - not for transfer rings */
1422 #define TRB_CMD_NOOP 23
1423 /* TRB IDs 24-31 reserved */
1424 /* Event TRBS */
1425 /* Transfer Event */
1426 #define TRB_TRANSFER 32
1427 /* Command Completion Event */
1428 #define TRB_COMPLETION 33
1429 /* Port Status Change Event */
1430 #define TRB_PORT_STATUS 34
1431 /* Bandwidth Request Event (opt) */
1432 #define TRB_BANDWIDTH_EVENT 35
1433 /* Doorbell Event (opt) */
1434 #define TRB_DOORBELL 36
1435 /* Host Controller Event */
1436 #define TRB_HC_EVENT 37
1437 /* Device Notification Event - device sent function wake notification */
1438 #define TRB_DEV_NOTE 38
1439 /* MFINDEX Wrap Event - microframe counter wrapped */
1440 #define TRB_MFINDEX_WRAP 39
1441 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1442 #define TRB_VENDOR_DEFINED_LOW 48
1443 /* Nec vendor-specific command completion event. */
1444 #define TRB_NEC_CMD_COMP 48
1445 /* Get NEC firmware revision. */
1446 #define TRB_NEC_GET_FW 49
1447
xhci_trb_type_string(u8 type)1448 static inline const char *xhci_trb_type_string(u8 type)
1449 {
1450 switch (type) {
1451 case TRB_NORMAL:
1452 return "Normal";
1453 case TRB_SETUP:
1454 return "Setup Stage";
1455 case TRB_DATA:
1456 return "Data Stage";
1457 case TRB_STATUS:
1458 return "Status Stage";
1459 case TRB_ISOC:
1460 return "Isoch";
1461 case TRB_LINK:
1462 return "Link";
1463 case TRB_EVENT_DATA:
1464 return "Event Data";
1465 case TRB_TR_NOOP:
1466 return "No-Op";
1467 case TRB_ENABLE_SLOT:
1468 return "Enable Slot Command";
1469 case TRB_DISABLE_SLOT:
1470 return "Disable Slot Command";
1471 case TRB_ADDR_DEV:
1472 return "Address Device Command";
1473 case TRB_CONFIG_EP:
1474 return "Configure Endpoint Command";
1475 case TRB_EVAL_CONTEXT:
1476 return "Evaluate Context Command";
1477 case TRB_RESET_EP:
1478 return "Reset Endpoint Command";
1479 case TRB_STOP_RING:
1480 return "Stop Ring Command";
1481 case TRB_SET_DEQ:
1482 return "Set TR Dequeue Pointer Command";
1483 case TRB_RESET_DEV:
1484 return "Reset Device Command";
1485 case TRB_FORCE_EVENT:
1486 return "Force Event Command";
1487 case TRB_NEG_BANDWIDTH:
1488 return "Negotiate Bandwidth Command";
1489 case TRB_SET_LT:
1490 return "Set Latency Tolerance Value Command";
1491 case TRB_GET_BW:
1492 return "Get Port Bandwidth Command";
1493 case TRB_FORCE_HEADER:
1494 return "Force Header Command";
1495 case TRB_CMD_NOOP:
1496 return "No-Op Command";
1497 case TRB_TRANSFER:
1498 return "Transfer Event";
1499 case TRB_COMPLETION:
1500 return "Command Completion Event";
1501 case TRB_PORT_STATUS:
1502 return "Port Status Change Event";
1503 case TRB_BANDWIDTH_EVENT:
1504 return "Bandwidth Request Event";
1505 case TRB_DOORBELL:
1506 return "Doorbell Event";
1507 case TRB_HC_EVENT:
1508 return "Host Controller Event";
1509 case TRB_DEV_NOTE:
1510 return "Device Notification Event";
1511 case TRB_MFINDEX_WRAP:
1512 return "MFINDEX Wrap Event";
1513 case TRB_NEC_CMD_COMP:
1514 return "NEC Command Completion Event";
1515 case TRB_NEC_GET_FW:
1516 return "NET Get Firmware Revision Command";
1517 default:
1518 return "UNKNOWN";
1519 }
1520 }
1521
1522 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1523 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1524 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1525 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1526 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1527 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1528
1529 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1530 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1531
1532 /*
1533 * TRBS_PER_SEGMENT must be a multiple of 4,
1534 * since the command ring is 64-byte aligned.
1535 * It must also be greater than 16.
1536 */
1537 #define TRBS_PER_SEGMENT 256
1538 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1539 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1540 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1541 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1542 /* TRB buffer pointers can't cross 64KB boundaries */
1543 #define TRB_MAX_BUFF_SHIFT 16
1544 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1545 /* How much data is left before the 64KB boundary? */
1546 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1547 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1548 #define MAX_SOFT_RETRY 3
1549 /*
1550 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if
1551 * XHCI_AVOID_BEI quirk is in use.
1552 */
1553 #define AVOID_BEI_INTERVAL_MIN 8
1554 #define AVOID_BEI_INTERVAL_MAX 32
1555
1556 struct xhci_segment {
1557 union xhci_trb *trbs;
1558 /* private to HCD */
1559 struct xhci_segment *next;
1560 unsigned int num;
1561 dma_addr_t dma;
1562 /* Max packet sized bounce buffer for td-fragmant alignment */
1563 dma_addr_t bounce_dma;
1564 void *bounce_buf;
1565 unsigned int bounce_offs;
1566 unsigned int bounce_len;
1567
1568 ANDROID_KABI_RESERVE(1);
1569 };
1570
1571 enum xhci_cancelled_td_status {
1572 TD_DIRTY = 0,
1573 TD_HALTED,
1574 TD_CLEARING_CACHE,
1575 TD_CLEARING_CACHE_DEFERRED,
1576 TD_CLEARED,
1577 };
1578
1579 struct xhci_td {
1580 struct list_head td_list;
1581 struct list_head cancelled_td_list;
1582 int status;
1583 enum xhci_cancelled_td_status cancel_status;
1584 struct urb *urb;
1585 struct xhci_segment *start_seg;
1586 union xhci_trb *first_trb;
1587 union xhci_trb *last_trb;
1588 struct xhci_segment *last_trb_seg;
1589 struct xhci_segment *bounce_seg;
1590 /* actual_length of the URB has already been set */
1591 bool urb_length_set;
1592 bool error_mid_td;
1593 unsigned int num_trbs;
1594 };
1595
1596 /*
1597 * xHCI command default timeout value in milliseconds.
1598 * USB 3.2 spec, section 9.2.6.1
1599 */
1600 #define XHCI_CMD_DEFAULT_TIMEOUT 5000
1601
1602 /* command descriptor */
1603 struct xhci_cd {
1604 struct xhci_command *command;
1605 union xhci_trb *cmd_trb;
1606 };
1607
1608 enum xhci_ring_type {
1609 TYPE_CTRL = 0,
1610 TYPE_ISOC,
1611 TYPE_BULK,
1612 TYPE_INTR,
1613 TYPE_STREAM,
1614 TYPE_COMMAND,
1615 TYPE_EVENT,
1616 };
1617
xhci_ring_type_string(enum xhci_ring_type type)1618 static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1619 {
1620 switch (type) {
1621 case TYPE_CTRL:
1622 return "CTRL";
1623 case TYPE_ISOC:
1624 return "ISOC";
1625 case TYPE_BULK:
1626 return "BULK";
1627 case TYPE_INTR:
1628 return "INTR";
1629 case TYPE_STREAM:
1630 return "STREAM";
1631 case TYPE_COMMAND:
1632 return "CMD";
1633 case TYPE_EVENT:
1634 return "EVENT";
1635 }
1636
1637 return "UNKNOWN";
1638 }
1639
1640 struct xhci_ring {
1641 struct xhci_segment *first_seg;
1642 struct xhci_segment *last_seg;
1643 union xhci_trb *enqueue;
1644 struct xhci_segment *enq_seg;
1645 union xhci_trb *dequeue;
1646 struct xhci_segment *deq_seg;
1647 struct list_head td_list;
1648 /*
1649 * Write the cycle state into the TRB cycle field to give ownership of
1650 * the TRB to the host controller (if we are the producer), or to check
1651 * if we own the TRB (if we are the consumer). See section 4.9.1.
1652 */
1653 u32 cycle_state;
1654 unsigned int stream_id;
1655 unsigned int num_segs;
1656 unsigned int num_trbs_free; /* used only by xhci DbC */
1657 unsigned int bounce_buf_len;
1658 enum xhci_ring_type type;
1659 bool last_td_was_short;
1660 struct radix_tree_root *trb_address_map;
1661
1662 ANDROID_KABI_RESERVE(1);
1663 ANDROID_KABI_RESERVE(2);
1664 };
1665
1666 struct xhci_erst_entry {
1667 /* 64-bit event ring segment address */
1668 __le64 seg_addr;
1669 __le32 seg_size;
1670 /* Set to zero */
1671 __le32 rsvd;
1672 };
1673
1674 struct xhci_erst {
1675 struct xhci_erst_entry *entries;
1676 unsigned int num_entries;
1677 /* xhci->event_ring keeps track of segment dma addresses */
1678 dma_addr_t erst_dma_addr;
1679 /* Num entries the ERST can contain */
1680 unsigned int erst_size;
1681
1682 ANDROID_KABI_RESERVE(1);
1683 };
1684
1685 struct xhci_scratchpad {
1686 u64 *sp_array;
1687 dma_addr_t sp_dma;
1688 void **sp_buffers;
1689 };
1690
1691 struct urb_priv {
1692 int num_tds;
1693 int num_tds_done;
1694 struct xhci_td td[];
1695 };
1696
1697 /*
1698 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1699 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1700 * meaning 64 ring segments.
1701 * Reasonable limit for number of Event Ring segments (spec allows 32k)
1702 */
1703 #define ERST_MAX_SEGS 2
1704 /* Poll every 60 seconds */
1705 #define POLL_TIMEOUT 60
1706 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1707 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1708 /* XXX: Make these module parameters */
1709
1710 struct s3_save {
1711 u32 command;
1712 u32 dev_nt;
1713 u64 dcbaa_ptr;
1714 u32 config_reg;
1715 };
1716
1717 /* Use for lpm */
1718 struct dev_info {
1719 u32 dev_id;
1720 struct list_head list;
1721 };
1722
1723 struct xhci_bus_state {
1724 unsigned long bus_suspended;
1725 unsigned long next_statechange;
1726
1727 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1728 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1729 u32 port_c_suspend;
1730 u32 suspended_ports;
1731 u32 port_remote_wakeup;
1732 /* which ports have started to resume */
1733 unsigned long resuming_ports;
1734 };
1735
1736 struct xhci_interrupter {
1737 struct xhci_ring *event_ring;
1738 struct xhci_erst erst;
1739 struct xhci_intr_reg __iomem *ir_set;
1740 unsigned int intr_num;
1741 bool ip_autoclear;
1742 bool skip_events;
1743 u32 isoc_bei_interval;
1744 /* For interrupter registers save and restore over suspend/resume */
1745 u32 s3_irq_pending;
1746 u32 s3_irq_control;
1747 u32 s3_erst_size;
1748 u64 s3_erst_base;
1749 u64 s3_erst_dequeue;
1750 };
1751 /*
1752 * It can take up to 20 ms to transition from RExit to U0 on the
1753 * Intel Lynx Point LP xHCI host.
1754 */
1755 #define XHCI_MAX_REXIT_TIMEOUT_MS 20
1756 struct xhci_port_cap {
1757 u32 *psi; /* array of protocol speed ID entries */
1758 u8 psi_count;
1759 u8 psi_uid_count;
1760 u8 maj_rev;
1761 u8 min_rev;
1762 };
1763
1764 struct xhci_port {
1765 __le32 __iomem *addr;
1766 int hw_portnum;
1767 int hcd_portnum;
1768 struct xhci_hub *rhub;
1769 struct xhci_port_cap *port_cap;
1770 unsigned int lpm_incapable:1;
1771 unsigned long resume_timestamp;
1772 bool rexit_active;
1773 struct completion rexit_done;
1774 struct completion u3exit_done;
1775 };
1776
1777 struct xhci_hub {
1778 struct xhci_port **ports;
1779 unsigned int num_ports;
1780 struct usb_hcd *hcd;
1781 /* keep track of bus suspend info */
1782 struct xhci_bus_state bus_state;
1783 /* supported prococol extended capabiliy values */
1784 u8 maj_rev;
1785 u8 min_rev;
1786 };
1787
1788 /* There is one xhci_hcd structure per controller */
1789 struct xhci_hcd {
1790 struct usb_hcd *main_hcd;
1791 struct usb_hcd *shared_hcd;
1792 /* glue to PCI and HCD framework */
1793 struct xhci_cap_regs __iomem *cap_regs;
1794 struct xhci_op_regs __iomem *op_regs;
1795 struct xhci_run_regs __iomem *run_regs;
1796 struct xhci_doorbell_array __iomem *dba;
1797
1798 /* Cached register copies of read-only HC data */
1799 __u32 hcs_params1;
1800 __u32 hcs_params2;
1801 __u32 hcs_params3;
1802 __u32 hcc_params;
1803 __u32 hcc_params2;
1804
1805 spinlock_t lock;
1806
1807 /* packed release number */
1808 u8 sbrn;
1809 u16 hci_version;
1810 u8 max_slots;
1811 u16 max_interrupters;
1812 u8 max_ports;
1813 u8 isoc_threshold;
1814 /* imod_interval in ns (I * 250ns) */
1815 u32 imod_interval;
1816 int event_ring_max;
1817 /* 4KB min, 128MB max */
1818 int page_size;
1819 /* Valid values are 12 to 20, inclusive */
1820 int page_shift;
1821 /* msi-x vectors */
1822 int msix_count;
1823 /* optional clocks */
1824 struct clk *clk;
1825 struct clk *reg_clk;
1826 /* optional reset controller */
1827 struct reset_control *reset;
1828 /* data structures */
1829 struct xhci_device_context_array *dcbaa;
1830 struct xhci_interrupter **interrupters;
1831 struct xhci_ring *cmd_ring;
1832 unsigned int cmd_ring_state;
1833 #define CMD_RING_STATE_RUNNING (1 << 0)
1834 #define CMD_RING_STATE_ABORTED (1 << 1)
1835 #define CMD_RING_STATE_STOPPED (1 << 2)
1836 struct list_head cmd_list;
1837 unsigned int cmd_ring_reserved_trbs;
1838 struct delayed_work cmd_timer;
1839 struct completion cmd_ring_stop_completion;
1840 struct xhci_command *current_cmd;
1841
1842 /* Scratchpad */
1843 struct xhci_scratchpad *scratchpad;
1844
1845 /* slot enabling and address device helpers */
1846 /* these are not thread safe so use mutex */
1847 struct mutex mutex;
1848 /* Internal mirror of the HW's dcbaa */
1849 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1850 /* For keeping track of bandwidth domains per roothub. */
1851 struct xhci_root_port_bw_info *rh_bw;
1852
1853 /* DMA pools */
1854 struct dma_pool *device_pool;
1855 struct dma_pool *segment_pool;
1856 struct dma_pool *small_streams_pool;
1857 struct dma_pool *medium_streams_pool;
1858
1859 /* Host controller watchdog timer structures */
1860 unsigned int xhc_state;
1861 unsigned long run_graceperiod;
1862 struct s3_save s3;
1863 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1864 *
1865 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1866 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1867 * that sees this status (other than the timer that set it) should stop touching
1868 * hardware immediately. Interrupt handlers should return immediately when
1869 * they see this status (any time they drop and re-acquire xhci->lock).
1870 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1871 * putting the TD on the canceled list, etc.
1872 *
1873 * There are no reports of xHCI host controllers that display this issue.
1874 */
1875 #define XHCI_STATE_DYING (1 << 0)
1876 #define XHCI_STATE_HALTED (1 << 1)
1877 #define XHCI_STATE_REMOVING (1 << 2)
1878 unsigned long long quirks;
1879 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1880 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
1881 #define XHCI_NEC_HOST BIT_ULL(2)
1882 #define XHCI_AMD_PLL_FIX BIT_ULL(3)
1883 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1884 /*
1885 * Certain Intel host controllers have a limit to the number of endpoint
1886 * contexts they can handle. Ideally, they would signal that they can't handle
1887 * anymore endpoint contexts by returning a Resource Error for the Configure
1888 * Endpoint command, but they don't. Instead they expect software to keep track
1889 * of the number of active endpoints for them, across configure endpoint
1890 * commands, reset device commands, disable slot commands, and address device
1891 * commands.
1892 */
1893 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1894 #define XHCI_BROKEN_MSI BIT_ULL(6)
1895 #define XHCI_RESET_ON_RESUME BIT_ULL(7)
1896 #define XHCI_SW_BW_CHECKING BIT_ULL(8)
1897 #define XHCI_AMD_0x96_HOST BIT_ULL(9)
1898 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1899 #define XHCI_LPM_SUPPORT BIT_ULL(11)
1900 #define XHCI_INTEL_HOST BIT_ULL(12)
1901 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1902 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1903 #define XHCI_AVOID_BEI BIT_ULL(15)
1904 #define XHCI_PLAT BIT_ULL(16) /* Deprecated */
1905 #define XHCI_SLOW_SUSPEND BIT_ULL(17)
1906 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1907 /* For controllers with a broken beyond repair streams implementation */
1908 #define XHCI_BROKEN_STREAMS BIT_ULL(19)
1909 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1910 #define XHCI_MTK_HOST BIT_ULL(21)
1911 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1912 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1913 #define XHCI_MISSING_CAS BIT_ULL(24)
1914 /* For controller with a broken Port Disable implementation */
1915 #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1916 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1917 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1918 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1919 #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1920 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
1921 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1922 #define XHCI_ZERO_64B_REGS BIT_ULL(32)
1923 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1924 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1925 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1926 #define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
1927 #define XHCI_SKIP_PHY_INIT BIT_ULL(37)
1928 #define XHCI_DISABLE_SPARSE BIT_ULL(38)
1929 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
1930 #define XHCI_NO_SOFT_RETRY BIT_ULL(40)
1931 #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41)
1932 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
1933 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
1934 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
1935 #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
1936 #define XHCI_ZHAOXIN_HOST BIT_ULL(46)
1937 #define XHCI_WRITE_64_HI_LO BIT_ULL(47)
1938
1939 unsigned int num_active_eps;
1940 unsigned int limit_active_eps;
1941 struct xhci_port *hw_ports;
1942 struct xhci_hub usb2_rhub;
1943 struct xhci_hub usb3_rhub;
1944 /* support xHCI 1.0 spec USB2 hardware LPM */
1945 unsigned hw_lpm_support:1;
1946 /* Broken Suspend flag for SNPS Suspend resume issue */
1947 unsigned broken_suspend:1;
1948 /* Indicates that omitting hcd is supported if root hub has no ports */
1949 unsigned allow_single_roothub:1;
1950 /* cached usb2 extened protocol capabilites */
1951 u32 *ext_caps;
1952 unsigned int num_ext_caps;
1953 /* cached extended protocol port capabilities */
1954 struct xhci_port_cap *port_caps;
1955 unsigned int num_port_caps;
1956 /* Compliance Mode Recovery Data */
1957 struct timer_list comp_mode_recovery_timer;
1958 u32 port_status_u0;
1959 u16 test_mode;
1960 /* Compliance Mode Timer Triggered every 2 seconds */
1961 #define COMP_MODE_RCVRY_MSECS 2000
1962
1963 struct dentry *debugfs_root;
1964 struct dentry *debugfs_slots;
1965 struct list_head regset_list;
1966
1967 void *dbc;
1968
1969 ANDROID_KABI_RESERVE(1);
1970 ANDROID_KABI_RESERVE(2);
1971 ANDROID_KABI_RESERVE(3);
1972 ANDROID_KABI_RESERVE(4);
1973
1974 /* platform-specific data -- must come last */
1975 unsigned long priv[] __aligned(sizeof(s64));
1976 };
1977
1978 /* Platform specific overrides to generic XHCI hc_driver ops */
1979 struct xhci_driver_overrides {
1980 size_t extra_priv_size;
1981 int (*reset)(struct usb_hcd *hcd);
1982 int (*start)(struct usb_hcd *hcd);
1983 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1984 struct usb_host_endpoint *ep);
1985 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1986 struct usb_host_endpoint *ep);
1987 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
1988 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
1989 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev,
1990 struct usb_tt *tt, gfp_t mem_flags);
1991 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1992 u16 wIndex, char *buf, u16 wLength);
1993
1994 ANDROID_KABI_RESERVE(1);
1995 ANDROID_KABI_RESERVE(2);
1996 ANDROID_KABI_RESERVE(3);
1997 ANDROID_KABI_RESERVE(4);
1998 };
1999
2000 #define XHCI_CFC_DELAY 10
2001
2002 /* convert between an HCD pointer and the corresponding EHCI_HCD */
hcd_to_xhci(struct usb_hcd * hcd)2003 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
2004 {
2005 struct usb_hcd *primary_hcd;
2006
2007 if (usb_hcd_is_primary_hcd(hcd))
2008 primary_hcd = hcd;
2009 else
2010 primary_hcd = hcd->primary_hcd;
2011
2012 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
2013 }
2014
xhci_to_hcd(struct xhci_hcd * xhci)2015 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
2016 {
2017 return xhci->main_hcd;
2018 }
2019
xhci_get_usb3_hcd(struct xhci_hcd * xhci)2020 static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci)
2021 {
2022 if (xhci->shared_hcd)
2023 return xhci->shared_hcd;
2024
2025 if (!xhci->usb2_rhub.num_ports)
2026 return xhci->main_hcd;
2027
2028 return NULL;
2029 }
2030
xhci_hcd_is_usb3(struct usb_hcd * hcd)2031 static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd)
2032 {
2033 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2034
2035 return hcd == xhci_get_usb3_hcd(xhci);
2036 }
2037
xhci_has_one_roothub(struct xhci_hcd * xhci)2038 static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci)
2039 {
2040 return xhci->allow_single_roothub &&
2041 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports);
2042 }
2043
2044 #define xhci_dbg(xhci, fmt, args...) \
2045 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2046 #define xhci_err(xhci, fmt, args...) \
2047 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2048 #define xhci_warn(xhci, fmt, args...) \
2049 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2050 #define xhci_warn_ratelimited(xhci, fmt, args...) \
2051 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2052 #define xhci_info(xhci, fmt, args...) \
2053 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2054
2055 /*
2056 * Registers should always be accessed with double word or quad word accesses.
2057 *
2058 * Some xHCI implementations may support 64-bit address pointers. Registers
2059 * with 64-bit address pointers should be written to with dword accesses by
2060 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
2061 * xHCI implementations that do not support 64-bit address pointers will ignore
2062 * the high dword, and write order is irrelevant.
2063 */
xhci_read_64(const struct xhci_hcd * xhci,__le64 __iomem * regs)2064 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
2065 __le64 __iomem *regs)
2066 {
2067 return lo_hi_readq(regs);
2068 }
xhci_write_64(struct xhci_hcd * xhci,const u64 val,__le64 __iomem * regs)2069 static inline void xhci_write_64(struct xhci_hcd *xhci,
2070 const u64 val, __le64 __iomem *regs)
2071 {
2072 lo_hi_writeq(val, regs);
2073 }
2074
xhci_link_trb_quirk(struct xhci_hcd * xhci)2075 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
2076 {
2077 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
2078 }
2079
2080 /* xHCI debugging */
2081 char *xhci_get_slot_state(struct xhci_hcd *xhci,
2082 struct xhci_container_ctx *ctx);
2083 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
2084 const char *fmt, ...);
2085
2086 /* xHCI memory management */
2087 void xhci_mem_cleanup(struct xhci_hcd *xhci);
2088 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
2089 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
2090 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
2091 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
2092 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
2093 struct usb_device *udev);
2094 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
2095 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
2096 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
2097 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2098 struct xhci_virt_device *virt_dev,
2099 int old_active_eps);
2100 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
2101 void xhci_update_bw_info(struct xhci_hcd *xhci,
2102 struct xhci_container_ctx *in_ctx,
2103 struct xhci_input_control_ctx *ctrl_ctx,
2104 struct xhci_virt_device *virt_dev);
2105 void xhci_endpoint_copy(struct xhci_hcd *xhci,
2106 struct xhci_container_ctx *in_ctx,
2107 struct xhci_container_ctx *out_ctx,
2108 unsigned int ep_index);
2109 void xhci_slot_copy(struct xhci_hcd *xhci,
2110 struct xhci_container_ctx *in_ctx,
2111 struct xhci_container_ctx *out_ctx);
2112 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
2113 struct usb_device *udev, struct usb_host_endpoint *ep,
2114 gfp_t mem_flags);
2115 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
2116 unsigned int num_segs, unsigned int cycle_state,
2117 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
2118 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
2119 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
2120 unsigned int num_trbs, gfp_t flags);
2121 void xhci_initialize_ring_info(struct xhci_ring *ring,
2122 unsigned int cycle_state);
2123 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
2124 struct xhci_virt_device *virt_dev,
2125 unsigned int ep_index);
2126 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
2127 unsigned int num_stream_ctxs,
2128 unsigned int num_streams,
2129 unsigned int max_packet, gfp_t flags);
2130 void xhci_free_stream_info(struct xhci_hcd *xhci,
2131 struct xhci_stream_info *stream_info);
2132 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2133 struct xhci_ep_ctx *ep_ctx,
2134 struct xhci_stream_info *stream_info);
2135 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2136 struct xhci_virt_ep *ep);
2137 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2138 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2139 struct xhci_ring *xhci_dma_to_transfer_ring(
2140 struct xhci_virt_ep *ep,
2141 u64 address);
2142 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2143 bool allocate_completion, gfp_t mem_flags);
2144 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2145 bool allocate_completion, gfp_t mem_flags);
2146 void xhci_urb_free_priv(struct urb_priv *urb_priv);
2147 void xhci_free_command(struct xhci_hcd *xhci,
2148 struct xhci_command *command);
2149 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2150 int type, gfp_t flags);
2151 void xhci_free_container_ctx(struct xhci_hcd *xhci,
2152 struct xhci_container_ctx *ctx);
2153 struct xhci_interrupter *
2154 xhci_create_secondary_interrupter(struct usb_hcd *hcd, int num_seg, int intr_num);
2155 void xhci_remove_secondary_interrupter(struct usb_hcd
2156 *hcd, struct xhci_interrupter *ir);
2157 void xhci_skip_sec_intr_events(struct xhci_hcd *xhci,
2158 struct xhci_ring *ring, struct xhci_interrupter *ir);
2159
2160 /* xHCI host controller glue */
2161 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2162 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
2163 void xhci_quiesce(struct xhci_hcd *xhci);
2164 int xhci_halt(struct xhci_hcd *xhci);
2165 int xhci_start(struct xhci_hcd *xhci);
2166 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
2167 int xhci_run(struct usb_hcd *hcd);
2168 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2169 void xhci_shutdown(struct usb_hcd *hcd);
2170 void xhci_stop(struct usb_hcd *hcd);
2171 void xhci_init_driver(struct hc_driver *drv,
2172 const struct xhci_driver_overrides *over);
2173 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2174 struct usb_host_endpoint *ep);
2175 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2176 struct usb_host_endpoint *ep);
2177 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2178 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2179 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
2180 struct usb_tt *tt, gfp_t mem_flags);
2181 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2182 int xhci_ext_cap_init(struct xhci_hcd *xhci);
2183
2184 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2185 int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg);
2186
2187 irqreturn_t xhci_irq(struct usb_hcd *hcd);
2188 irqreturn_t xhci_msi_irq(int irq, void *hcd);
2189 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2190 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2191 struct xhci_virt_device *virt_dev,
2192 struct usb_device *hdev,
2193 struct usb_tt *tt, gfp_t mem_flags);
2194 int xhci_enable_interrupter(struct xhci_interrupter *ir);
2195 int xhci_disable_interrupter(struct xhci_interrupter *ir);
2196 int xhci_set_interrupter_moderation(struct xhci_interrupter *ir,
2197 u32 imod_interval);
2198
2199 /* xHCI ring, segment, TRB, and TD functions */
2200 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2201 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2202 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2203 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2204 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2205 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2206 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2207 u32 trb_type, u32 slot_id);
2208 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2209 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2210 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2211 u32 field1, u32 field2, u32 field3, u32 field4);
2212 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2213 int slot_id, unsigned int ep_index, int suspend);
2214 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2215 int slot_id, unsigned int ep_index);
2216 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2217 int slot_id, unsigned int ep_index);
2218 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2219 int slot_id, unsigned int ep_index);
2220 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2221 struct urb *urb, int slot_id, unsigned int ep_index);
2222 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2223 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2224 bool command_must_succeed);
2225 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2226 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2227 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2228 int slot_id, unsigned int ep_index,
2229 enum xhci_ep_reset_type reset_type);
2230 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2231 u32 slot_id);
2232 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
2233 unsigned int ep_index, unsigned int stream_id,
2234 struct xhci_td *td);
2235 void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2236 void xhci_handle_command_timeout(struct work_struct *work);
2237
2238 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2239 unsigned int ep_index, unsigned int stream_id);
2240 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
2241 unsigned int slot_id,
2242 unsigned int ep_index);
2243 void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2244 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2245 unsigned int count_trbs(u64 addr, u64 len);
2246 int xhci_stop_endpoint_sync(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2247 int suspend, gfp_t gfp_flags);
2248 void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
2249 struct xhci_interrupter *ir,
2250 bool clear_ehb);
2251
2252 /* xHCI roothub code */
2253 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
2254 u32 link_state);
2255 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
2256 u32 port_bit);
2257 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2258 char *buf, u16 wLength);
2259 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2260 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2261 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
2262
2263 void xhci_hc_died(struct xhci_hcd *xhci);
2264
2265 #ifdef CONFIG_PM
2266 int xhci_bus_suspend(struct usb_hcd *hcd);
2267 int xhci_bus_resume(struct usb_hcd *hcd);
2268 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
2269 #else
2270 #define xhci_bus_suspend NULL
2271 #define xhci_bus_resume NULL
2272 #define xhci_get_resuming_ports NULL
2273 #endif /* CONFIG_PM */
2274
2275 u32 xhci_port_state_to_neutral(u32 state);
2276 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2277 u16 port);
2278 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2279
2280 /* xHCI contexts */
2281 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2282 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2283 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2284
2285 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2286 unsigned int slot_id, unsigned int ep_index,
2287 unsigned int stream_id);
2288
xhci_urb_to_transfer_ring(struct xhci_hcd * xhci,struct urb * urb)2289 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2290 struct urb *urb)
2291 {
2292 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2293 xhci_get_endpoint_index(&urb->ep->desc),
2294 urb->stream_id);
2295 }
2296
2297 /*
2298 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
2299 * them anyways as we where unable to find a device that matches the
2300 * constraints.
2301 */
xhci_urb_suitable_for_idt(struct urb * urb)2302 static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
2303 {
2304 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
2305 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
2306 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
2307 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
2308 !urb->num_sgs)
2309 return true;
2310
2311 return false;
2312 }
2313
xhci_slot_state_string(u32 state)2314 static inline char *xhci_slot_state_string(u32 state)
2315 {
2316 switch (state) {
2317 case SLOT_STATE_ENABLED:
2318 return "enabled/disabled";
2319 case SLOT_STATE_DEFAULT:
2320 return "default";
2321 case SLOT_STATE_ADDRESSED:
2322 return "addressed";
2323 case SLOT_STATE_CONFIGURED:
2324 return "configured";
2325 default:
2326 return "reserved";
2327 }
2328 }
2329
xhci_decode_trb(char * str,size_t size,u32 field0,u32 field1,u32 field2,u32 field3)2330 static inline const char *xhci_decode_trb(char *str, size_t size,
2331 u32 field0, u32 field1, u32 field2, u32 field3)
2332 {
2333 int type = TRB_FIELD_TO_TYPE(field3);
2334
2335 switch (type) {
2336 case TRB_LINK:
2337 snprintf(str, size,
2338 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2339 field1, field0, GET_INTR_TARGET(field2),
2340 xhci_trb_type_string(type),
2341 field3 & TRB_IOC ? 'I' : 'i',
2342 field3 & TRB_CHAIN ? 'C' : 'c',
2343 field3 & TRB_TC ? 'T' : 't',
2344 field3 & TRB_CYCLE ? 'C' : 'c');
2345 break;
2346 case TRB_TRANSFER:
2347 case TRB_COMPLETION:
2348 case TRB_PORT_STATUS:
2349 case TRB_BANDWIDTH_EVENT:
2350 case TRB_DOORBELL:
2351 case TRB_HC_EVENT:
2352 case TRB_DEV_NOTE:
2353 case TRB_MFINDEX_WRAP:
2354 snprintf(str, size,
2355 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2356 field1, field0,
2357 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2358 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2359 /* Macro decrements 1, maybe it shouldn't?!? */
2360 TRB_TO_EP_INDEX(field3) + 1,
2361 xhci_trb_type_string(type),
2362 field3 & EVENT_DATA ? 'E' : 'e',
2363 field3 & TRB_CYCLE ? 'C' : 'c');
2364
2365 break;
2366 case TRB_SETUP:
2367 snprintf(str, size,
2368 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2369 field0 & 0xff,
2370 (field0 & 0xff00) >> 8,
2371 (field0 & 0xff000000) >> 24,
2372 (field0 & 0xff0000) >> 16,
2373 (field1 & 0xff00) >> 8,
2374 field1 & 0xff,
2375 (field1 & 0xff000000) >> 16 |
2376 (field1 & 0xff0000) >> 16,
2377 TRB_LEN(field2), GET_TD_SIZE(field2),
2378 GET_INTR_TARGET(field2),
2379 xhci_trb_type_string(type),
2380 field3 & TRB_IDT ? 'I' : 'i',
2381 field3 & TRB_IOC ? 'I' : 'i',
2382 field3 & TRB_CYCLE ? 'C' : 'c');
2383 break;
2384 case TRB_DATA:
2385 snprintf(str, size,
2386 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2387 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2388 GET_INTR_TARGET(field2),
2389 xhci_trb_type_string(type),
2390 field3 & TRB_IDT ? 'I' : 'i',
2391 field3 & TRB_IOC ? 'I' : 'i',
2392 field3 & TRB_CHAIN ? 'C' : 'c',
2393 field3 & TRB_NO_SNOOP ? 'S' : 's',
2394 field3 & TRB_ISP ? 'I' : 'i',
2395 field3 & TRB_ENT ? 'E' : 'e',
2396 field3 & TRB_CYCLE ? 'C' : 'c');
2397 break;
2398 case TRB_STATUS:
2399 snprintf(str, size,
2400 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2401 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2402 GET_INTR_TARGET(field2),
2403 xhci_trb_type_string(type),
2404 field3 & TRB_IOC ? 'I' : 'i',
2405 field3 & TRB_CHAIN ? 'C' : 'c',
2406 field3 & TRB_ENT ? 'E' : 'e',
2407 field3 & TRB_CYCLE ? 'C' : 'c');
2408 break;
2409 case TRB_NORMAL:
2410 case TRB_ISOC:
2411 case TRB_EVENT_DATA:
2412 case TRB_TR_NOOP:
2413 snprintf(str, size,
2414 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2415 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2416 GET_INTR_TARGET(field2),
2417 xhci_trb_type_string(type),
2418 field3 & TRB_BEI ? 'B' : 'b',
2419 field3 & TRB_IDT ? 'I' : 'i',
2420 field3 & TRB_IOC ? 'I' : 'i',
2421 field3 & TRB_CHAIN ? 'C' : 'c',
2422 field3 & TRB_NO_SNOOP ? 'S' : 's',
2423 field3 & TRB_ISP ? 'I' : 'i',
2424 field3 & TRB_ENT ? 'E' : 'e',
2425 field3 & TRB_CYCLE ? 'C' : 'c');
2426 break;
2427
2428 case TRB_CMD_NOOP:
2429 case TRB_ENABLE_SLOT:
2430 snprintf(str, size,
2431 "%s: flags %c",
2432 xhci_trb_type_string(type),
2433 field3 & TRB_CYCLE ? 'C' : 'c');
2434 break;
2435 case TRB_DISABLE_SLOT:
2436 case TRB_NEG_BANDWIDTH:
2437 snprintf(str, size,
2438 "%s: slot %d flags %c",
2439 xhci_trb_type_string(type),
2440 TRB_TO_SLOT_ID(field3),
2441 field3 & TRB_CYCLE ? 'C' : 'c');
2442 break;
2443 case TRB_ADDR_DEV:
2444 snprintf(str, size,
2445 "%s: ctx %08x%08x slot %d flags %c:%c",
2446 xhci_trb_type_string(type),
2447 field1, field0,
2448 TRB_TO_SLOT_ID(field3),
2449 field3 & TRB_BSR ? 'B' : 'b',
2450 field3 & TRB_CYCLE ? 'C' : 'c');
2451 break;
2452 case TRB_CONFIG_EP:
2453 snprintf(str, size,
2454 "%s: ctx %08x%08x slot %d flags %c:%c",
2455 xhci_trb_type_string(type),
2456 field1, field0,
2457 TRB_TO_SLOT_ID(field3),
2458 field3 & TRB_DC ? 'D' : 'd',
2459 field3 & TRB_CYCLE ? 'C' : 'c');
2460 break;
2461 case TRB_EVAL_CONTEXT:
2462 snprintf(str, size,
2463 "%s: ctx %08x%08x slot %d flags %c",
2464 xhci_trb_type_string(type),
2465 field1, field0,
2466 TRB_TO_SLOT_ID(field3),
2467 field3 & TRB_CYCLE ? 'C' : 'c');
2468 break;
2469 case TRB_RESET_EP:
2470 snprintf(str, size,
2471 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2472 xhci_trb_type_string(type),
2473 field1, field0,
2474 TRB_TO_SLOT_ID(field3),
2475 /* Macro decrements 1, maybe it shouldn't?!? */
2476 TRB_TO_EP_INDEX(field3) + 1,
2477 field3 & TRB_TSP ? 'T' : 't',
2478 field3 & TRB_CYCLE ? 'C' : 'c');
2479 break;
2480 case TRB_STOP_RING:
2481 snprintf(str, size,
2482 "%s: slot %d sp %d ep %d flags %c",
2483 xhci_trb_type_string(type),
2484 TRB_TO_SLOT_ID(field3),
2485 TRB_TO_SUSPEND_PORT(field3),
2486 /* Macro decrements 1, maybe it shouldn't?!? */
2487 TRB_TO_EP_INDEX(field3) + 1,
2488 field3 & TRB_CYCLE ? 'C' : 'c');
2489 break;
2490 case TRB_SET_DEQ:
2491 snprintf(str, size,
2492 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2493 xhci_trb_type_string(type),
2494 field1, field0,
2495 TRB_TO_STREAM_ID(field2),
2496 TRB_TO_SLOT_ID(field3),
2497 /* Macro decrements 1, maybe it shouldn't?!? */
2498 TRB_TO_EP_INDEX(field3) + 1,
2499 field3 & TRB_CYCLE ? 'C' : 'c');
2500 break;
2501 case TRB_RESET_DEV:
2502 snprintf(str, size,
2503 "%s: slot %d flags %c",
2504 xhci_trb_type_string(type),
2505 TRB_TO_SLOT_ID(field3),
2506 field3 & TRB_CYCLE ? 'C' : 'c');
2507 break;
2508 case TRB_FORCE_EVENT:
2509 snprintf(str, size,
2510 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2511 xhci_trb_type_string(type),
2512 field1, field0,
2513 TRB_TO_VF_INTR_TARGET(field2),
2514 TRB_TO_VF_ID(field3),
2515 field3 & TRB_CYCLE ? 'C' : 'c');
2516 break;
2517 case TRB_SET_LT:
2518 snprintf(str, size,
2519 "%s: belt %d flags %c",
2520 xhci_trb_type_string(type),
2521 TRB_TO_BELT(field3),
2522 field3 & TRB_CYCLE ? 'C' : 'c');
2523 break;
2524 case TRB_GET_BW:
2525 snprintf(str, size,
2526 "%s: ctx %08x%08x slot %d speed %d flags %c",
2527 xhci_trb_type_string(type),
2528 field1, field0,
2529 TRB_TO_SLOT_ID(field3),
2530 TRB_TO_DEV_SPEED(field3),
2531 field3 & TRB_CYCLE ? 'C' : 'c');
2532 break;
2533 case TRB_FORCE_HEADER:
2534 snprintf(str, size,
2535 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2536 xhci_trb_type_string(type),
2537 field2, field1, field0 & 0xffffffe0,
2538 TRB_TO_PACKET_TYPE(field0),
2539 TRB_TO_ROOTHUB_PORT(field3),
2540 field3 & TRB_CYCLE ? 'C' : 'c');
2541 break;
2542 default:
2543 snprintf(str, size,
2544 "type '%s' -> raw %08x %08x %08x %08x",
2545 xhci_trb_type_string(type),
2546 field0, field1, field2, field3);
2547 }
2548
2549 return str;
2550 }
2551
xhci_decode_ctrl_ctx(char * str,unsigned long drop,unsigned long add)2552 static inline const char *xhci_decode_ctrl_ctx(char *str,
2553 unsigned long drop, unsigned long add)
2554 {
2555 unsigned int bit;
2556 int ret = 0;
2557
2558 str[0] = '\0';
2559
2560 if (drop) {
2561 ret = sprintf(str, "Drop:");
2562 for_each_set_bit(bit, &drop, 32)
2563 ret += sprintf(str + ret, " %d%s",
2564 bit / 2,
2565 bit % 2 ? "in":"out");
2566 ret += sprintf(str + ret, ", ");
2567 }
2568
2569 if (add) {
2570 ret += sprintf(str + ret, "Add:%s%s",
2571 (add & SLOT_FLAG) ? " slot":"",
2572 (add & EP0_FLAG) ? " ep0":"");
2573 add &= ~(SLOT_FLAG | EP0_FLAG);
2574 for_each_set_bit(bit, &add, 32)
2575 ret += sprintf(str + ret, " %d%s",
2576 bit / 2,
2577 bit % 2 ? "in":"out");
2578 }
2579 return str;
2580 }
2581
xhci_decode_slot_context(char * str,u32 info,u32 info2,u32 tt_info,u32 state)2582 static inline const char *xhci_decode_slot_context(char *str,
2583 u32 info, u32 info2, u32 tt_info, u32 state)
2584 {
2585 u32 speed;
2586 u32 hub;
2587 u32 mtt;
2588 int ret = 0;
2589
2590 speed = info & DEV_SPEED;
2591 hub = info & DEV_HUB;
2592 mtt = info & DEV_MTT;
2593
2594 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2595 info & ROUTE_STRING_MASK,
2596 ({ char *s;
2597 switch (speed) {
2598 case SLOT_SPEED_FS:
2599 s = "full-speed";
2600 break;
2601 case SLOT_SPEED_LS:
2602 s = "low-speed";
2603 break;
2604 case SLOT_SPEED_HS:
2605 s = "high-speed";
2606 break;
2607 case SLOT_SPEED_SS:
2608 s = "super-speed";
2609 break;
2610 case SLOT_SPEED_SSP:
2611 s = "super-speed plus";
2612 break;
2613 default:
2614 s = "UNKNOWN speed";
2615 } s; }),
2616 mtt ? " multi-TT" : "",
2617 hub ? " Hub" : "",
2618 (info & LAST_CTX_MASK) >> 27,
2619 info2 & MAX_EXIT,
2620 DEVINFO_TO_ROOT_HUB_PORT(info2),
2621 DEVINFO_TO_MAX_PORTS(info2));
2622
2623 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2624 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2625 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2626 state & DEV_ADDR_MASK,
2627 xhci_slot_state_string(GET_SLOT_STATE(state)));
2628
2629 return str;
2630 }
2631
2632
xhci_portsc_link_state_string(u32 portsc)2633 static inline const char *xhci_portsc_link_state_string(u32 portsc)
2634 {
2635 switch (portsc & PORT_PLS_MASK) {
2636 case XDEV_U0:
2637 return "U0";
2638 case XDEV_U1:
2639 return "U1";
2640 case XDEV_U2:
2641 return "U2";
2642 case XDEV_U3:
2643 return "U3";
2644 case XDEV_DISABLED:
2645 return "Disabled";
2646 case XDEV_RXDETECT:
2647 return "RxDetect";
2648 case XDEV_INACTIVE:
2649 return "Inactive";
2650 case XDEV_POLLING:
2651 return "Polling";
2652 case XDEV_RECOVERY:
2653 return "Recovery";
2654 case XDEV_HOT_RESET:
2655 return "Hot Reset";
2656 case XDEV_COMP_MODE:
2657 return "Compliance mode";
2658 case XDEV_TEST_MODE:
2659 return "Test mode";
2660 case XDEV_RESUME:
2661 return "Resume";
2662 default:
2663 break;
2664 }
2665 return "Unknown";
2666 }
2667
xhci_decode_portsc(char * str,u32 portsc)2668 static inline const char *xhci_decode_portsc(char *str, u32 portsc)
2669 {
2670 int ret;
2671
2672 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2673 portsc & PORT_POWER ? "Powered" : "Powered-off",
2674 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2675 portsc & PORT_PE ? "Enabled" : "Disabled",
2676 xhci_portsc_link_state_string(portsc),
2677 DEV_PORT_SPEED(portsc));
2678
2679 if (portsc & PORT_OC)
2680 ret += sprintf(str + ret, "OverCurrent ");
2681 if (portsc & PORT_RESET)
2682 ret += sprintf(str + ret, "In-Reset ");
2683
2684 ret += sprintf(str + ret, "Change: ");
2685 if (portsc & PORT_CSC)
2686 ret += sprintf(str + ret, "CSC ");
2687 if (portsc & PORT_PEC)
2688 ret += sprintf(str + ret, "PEC ");
2689 if (portsc & PORT_WRC)
2690 ret += sprintf(str + ret, "WRC ");
2691 if (portsc & PORT_OCC)
2692 ret += sprintf(str + ret, "OCC ");
2693 if (portsc & PORT_RC)
2694 ret += sprintf(str + ret, "PRC ");
2695 if (portsc & PORT_PLC)
2696 ret += sprintf(str + ret, "PLC ");
2697 if (portsc & PORT_CEC)
2698 ret += sprintf(str + ret, "CEC ");
2699 if (portsc & PORT_CAS)
2700 ret += sprintf(str + ret, "CAS ");
2701
2702 ret += sprintf(str + ret, "Wake: ");
2703 if (portsc & PORT_WKCONN_E)
2704 ret += sprintf(str + ret, "WCE ");
2705 if (portsc & PORT_WKDISC_E)
2706 ret += sprintf(str + ret, "WDE ");
2707 if (portsc & PORT_WKOC_E)
2708 ret += sprintf(str + ret, "WOE ");
2709
2710 return str;
2711 }
2712
xhci_decode_usbsts(char * str,u32 usbsts)2713 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts)
2714 {
2715 int ret = 0;
2716
2717 ret = sprintf(str, " 0x%08x", usbsts);
2718
2719 if (usbsts == ~(u32)0)
2720 return str;
2721
2722 if (usbsts & STS_HALT)
2723 ret += sprintf(str + ret, " HCHalted");
2724 if (usbsts & STS_FATAL)
2725 ret += sprintf(str + ret, " HSE");
2726 if (usbsts & STS_EINT)
2727 ret += sprintf(str + ret, " EINT");
2728 if (usbsts & STS_PORT)
2729 ret += sprintf(str + ret, " PCD");
2730 if (usbsts & STS_SAVE)
2731 ret += sprintf(str + ret, " SSS");
2732 if (usbsts & STS_RESTORE)
2733 ret += sprintf(str + ret, " RSS");
2734 if (usbsts & STS_SRE)
2735 ret += sprintf(str + ret, " SRE");
2736 if (usbsts & STS_CNR)
2737 ret += sprintf(str + ret, " CNR");
2738 if (usbsts & STS_HCE)
2739 ret += sprintf(str + ret, " HCE");
2740
2741 return str;
2742 }
2743
xhci_decode_doorbell(char * str,u32 slot,u32 doorbell)2744 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell)
2745 {
2746 u8 ep;
2747 u16 stream;
2748 int ret;
2749
2750 ep = (doorbell & 0xff);
2751 stream = doorbell >> 16;
2752
2753 if (slot == 0) {
2754 sprintf(str, "Command Ring %d", doorbell);
2755 return str;
2756 }
2757 ret = sprintf(str, "Slot %d ", slot);
2758 if (ep > 0 && ep < 32)
2759 ret = sprintf(str + ret, "ep%d%s",
2760 ep / 2,
2761 ep % 2 ? "in" : "out");
2762 else if (ep == 0 || ep < 248)
2763 ret = sprintf(str + ret, "Reserved %d", ep);
2764 else
2765 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2766 if (stream)
2767 ret = sprintf(str + ret, " Stream %d", stream);
2768
2769 return str;
2770 }
2771
xhci_ep_state_string(u8 state)2772 static inline const char *xhci_ep_state_string(u8 state)
2773 {
2774 switch (state) {
2775 case EP_STATE_DISABLED:
2776 return "disabled";
2777 case EP_STATE_RUNNING:
2778 return "running";
2779 case EP_STATE_HALTED:
2780 return "halted";
2781 case EP_STATE_STOPPED:
2782 return "stopped";
2783 case EP_STATE_ERROR:
2784 return "error";
2785 default:
2786 return "INVALID";
2787 }
2788 }
2789
xhci_ep_type_string(u8 type)2790 static inline const char *xhci_ep_type_string(u8 type)
2791 {
2792 switch (type) {
2793 case ISOC_OUT_EP:
2794 return "Isoc OUT";
2795 case BULK_OUT_EP:
2796 return "Bulk OUT";
2797 case INT_OUT_EP:
2798 return "Int OUT";
2799 case CTRL_EP:
2800 return "Ctrl";
2801 case ISOC_IN_EP:
2802 return "Isoc IN";
2803 case BULK_IN_EP:
2804 return "Bulk IN";
2805 case INT_IN_EP:
2806 return "Int IN";
2807 default:
2808 return "INVALID";
2809 }
2810 }
2811
xhci_decode_ep_context(char * str,u32 info,u32 info2,u64 deq,u32 tx_info)2812 static inline const char *xhci_decode_ep_context(char *str, u32 info,
2813 u32 info2, u64 deq, u32 tx_info)
2814 {
2815 int ret;
2816
2817 u32 esit;
2818 u16 maxp;
2819 u16 avg;
2820
2821 u8 max_pstr;
2822 u8 ep_state;
2823 u8 interval;
2824 u8 ep_type;
2825 u8 burst;
2826 u8 cerr;
2827 u8 mult;
2828
2829 bool lsa;
2830 bool hid;
2831
2832 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2833 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2834
2835 ep_state = info & EP_STATE_MASK;
2836 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2837 interval = CTX_TO_EP_INTERVAL(info);
2838 mult = CTX_TO_EP_MULT(info) + 1;
2839 lsa = !!(info & EP_HAS_LSA);
2840
2841 cerr = (info2 & (3 << 1)) >> 1;
2842 ep_type = CTX_TO_EP_TYPE(info2);
2843 hid = !!(info2 & (1 << 7));
2844 burst = CTX_TO_MAX_BURST(info2);
2845 maxp = MAX_PACKET_DECODED(info2);
2846
2847 avg = EP_AVG_TRB_LENGTH(tx_info);
2848
2849 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2850 xhci_ep_state_string(ep_state), mult,
2851 max_pstr, lsa ? "LSA " : "");
2852
2853 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2854 (1 << interval) * 125, esit, cerr);
2855
2856 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2857 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2858 burst, maxp, deq);
2859
2860 ret += sprintf(str + ret, "avg trb len %d", avg);
2861
2862 return str;
2863 }
2864
2865 #endif /* __LINUX_XHCI_HCD_H */
2866