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Searched refs:CP_ME1_PIPE2_INT_CNTL (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/radeon/
Dcikd.h1360 #define CP_ME1_PIPE2_INT_CNTL 0xC21C macro
Dcik.c6870 WREG32(CP_ME1_PIPE2_INT_CNTL, 0); in cik_disable_interrupt_state()
7053 cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7224 WREG32(CP_ME1_PIPE2_INT_CNTL, cp_m1p2); in cik_irq_set()
/drivers/gpu/drm/amd/amdgpu/
Dgfx_v8_0.c6558 WREG32_FIELD(CP_ME1_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()