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Searched refs:CP_PQ_WPTR_POLL_CNTL (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/radeon/
Dcikd.h1355 #define CP_PQ_WPTR_POLL_CNTL 0xC20C macro
Dcik.c4191 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL); in cik_compute_stop()
4193 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); in cik_compute_stop()
4610 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL); in cik_cp_compute_resume()
4612 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); in cik_cp_compute_resume()
/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_4_3.c1606 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_4_3_xcc_kiq_init_register()
1987 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_4_3_xcc_fini()
Dgfx_v9_0.c3383 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_0_kiq_init_register()
3792 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_0_hw_fini()
Dgfx_v7_0.c2983 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v7_0_mqd_commit()
Dgfx_v11_0.c3879 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v11_0_kiq_init_register()
Dgfx_v8_0.c4568 WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v8_0_mqd_commit()
Dgfx_v10_0.c6625 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v10_0_kiq_init_register()