Searched refs:CP_RB0_CNTL (Results 1 – 11 of 11) sorted by relevance
| /drivers/gpu/drm/radeon/ |
| D | nid.h | 484 #define CP_RB0_CNTL 0xC104 macro
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| D | sid.h | 1246 #define CP_RB0_CNTL 0xC104 macro
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| D | cikd.h | 1302 #define CP_RB0_CNTL 0xC104 macro
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| D | si.c | 3673 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3676 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3692 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
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| D | ni.c | 1619 CP_RB0_CNTL, in cayman_cp_resume()
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| D | cik.c | 4074 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4077 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in cik_cp_gfx_resume()
4092 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v8_0.c | 4253 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
4254 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v8_0_cp_gfx_resume()
4255 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3); in gfx_v8_0_cp_gfx_resume()
4256 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1); in gfx_v8_0_cp_gfx_resume()
4258 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v8_0_cp_gfx_resume()
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| D | sid.h | 1274 #define CP_RB0_CNTL 0x3041 macro
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| D | gfx_v9_0.c | 3109 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v9_0_cp_gfx_resume()
3110 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v9_0_cp_gfx_resume()
3112 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v9_0_cp_gfx_resume()
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| D | gfx_v11_0.c | 3258 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3259 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
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| D | gfx_v10_0.c | 6102 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
6103 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
6105 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v10_0_cp_gfx_resume()
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