Searched refs:DEBUGFS_REG32 (Results 1 – 4 of 4) sorted by relevance
/drivers/gpu/drm/tegra/ |
D | hdmi.c | 890 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } macro 893 DEBUGFS_REG32(HDMI_CTXSW), 894 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0), 895 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1), 896 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2), 897 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB), 898 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB), 899 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB), 900 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB), 901 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB), [all …]
|
D | dc.c | 1420 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } macro 1423 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT), 1424 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL), 1425 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR), 1426 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT), 1427 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL), 1428 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR), 1429 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT), 1430 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL), 1431 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR), [all …]
|
D | dsi.c | 123 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } macro 126 DEBUGFS_REG32(DSI_INCR_SYNCPT), 127 DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL), 128 DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR), 129 DEBUGFS_REG32(DSI_CTXSW), 130 DEBUGFS_REG32(DSI_RD_DATA), 131 DEBUGFS_REG32(DSI_WR_DATA), 132 DEBUGFS_REG32(DSI_POWER_CONTROL), 133 DEBUGFS_REG32(DSI_INT_ENABLE), 134 DEBUGFS_REG32(DSI_INT_STATUS), [all …]
|
D | sor.c | 1530 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } macro 1533 DEBUGFS_REG32(SOR_CTXSW), 1534 DEBUGFS_REG32(SOR_SUPER_STATE0), 1535 DEBUGFS_REG32(SOR_SUPER_STATE1), 1536 DEBUGFS_REG32(SOR_STATE0), 1537 DEBUGFS_REG32(SOR_STATE1), 1538 DEBUGFS_REG32(SOR_HEAD_STATE0(0)), 1539 DEBUGFS_REG32(SOR_HEAD_STATE0(1)), 1540 DEBUGFS_REG32(SOR_HEAD_STATE1(0)), 1541 DEBUGFS_REG32(SOR_HEAD_STATE1(1)), [all …]
|