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Searched refs:DISABLE_MEM_PWR_CTRL (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_5_1_enum.h1056 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
Dbif_5_0_enum.h1186 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_8_0_enum.h1056 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
Dsmu_7_1_3_enum.h1270 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
Dsmu_7_1_2_enum.h1234 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_8_2_enum.h1056 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
Dgmc_8_1_enum.h1186 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_enum.h1069 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
Duvd_5_0_enum.h1199 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_3_0_enum.h1485 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
Doss_3_0_1_enum.h1452 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_10_0_enum.h1761 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
Ddce_11_0_enum.h5628 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
Ddce_11_2_enum.h6266 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_enum.h6846 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
Dgfx_8_1_enum.h6796 DISABLE_MEM_PWR_CTRL = 0x1, enumerator
/drivers/gpu/drm/amd/include/
Dvega10_enum.h205 DISABLE_MEM_PWR_CTRL = 0x00000001, enumerator
Dsoc21_enum.h10973 DISABLE_MEM_PWR_CTRL = 0x00000001, enumerator
Dnavi10_enum.h9540 DISABLE_MEM_PWR_CTRL = 0x00000001, enumerator