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Searched refs:DPMTABLE_OD_UPDATE_SCLK (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/radeon/
Dci_dpm.h189 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 macro
Dci_dpm.c1426 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_unfreeze_sclk_mclk_dpm()
1534 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_freeze_sclk_mclk_dpm()
3835 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3871 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3877 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega12_hwmgr.h174 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 macro
Dvega20_hwmgr.h228 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 macro
Dsmu7_hwmgr.c1022 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in smu7_check_dpm_table_updated()
1049 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; in smu7_check_dpm_table_updated()
1055 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; in smu7_check_dpm_table_updated()
1726 } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { in smu7_update_avfs()
4101 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in smu7_find_dpm_states_clocks_in_dpm_table()
4215 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in smu7_freeze_sclk_mclk_dpm()
4257 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4272 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4371 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in smu7_unfreeze_sclk_mclk_dpm()
4743 *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | in smu7_check_states_equal()
Dvega10_hwmgr.c1625 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in vega10_populate_single_gfx_level()
2533 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; in vega10_check_dpm_table_updated()
2567 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; in vega10_init_smc_table()
3439 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in vega10_find_dpm_states_clocks_in_dpm_table()
3475 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3487 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_SOCCLK)) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()
5580 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in vega10_odn_edit_dpm_table()
/drivers/gpu/drm/amd/pm/powerplay/inc/
Dhardwaremanager.h376 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 macro
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dvegam_smumgr.c2204 (DPMTABLE_OD_UPDATE_SCLK + in vegam_program_mem_timing_parameters()
Diceland_smumgr.c2168 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK)) in iceland_program_mem_timing_parameters()
Dfiji_smumgr.c2255 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in fiji_program_mem_timing_parameters()
Dpolaris10_smumgr.c2139 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in polaris10_program_mem_timing_parameters()
Dtonga_smumgr.c2557 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK)) in tonga_program_mem_timing_parameters()
Dci_smumgr.c2205 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK)) in ci_program_mem_timing_parameters()