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Searched refs:DP_TP_CTL (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_fdi.c791 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
850 intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0); in hsw_fdi_link_train()
851 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
863 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
Dintel_ddi.c2182 return DP_TP_CTL(encoder->port); in dp_tp_ctl_reg()
/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c518 MMIO_D(DP_TP_CTL(PORT_A)); in iterate_generic_mmio()
519 MMIO_D(DP_TP_CTL(PORT_B)); in iterate_generic_mmio()
520 MMIO_D(DP_TP_CTL(PORT_C)); in iterate_generic_mmio()
521 MMIO_D(DP_TP_CTL(PORT_D)); in iterate_generic_mmio()
522 MMIO_D(DP_TP_CTL(PORT_E)); in iterate_generic_mmio()
Di915_reg.h5688 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) macro
/drivers/gpu/drm/i915/gvt/
Dhandlers.c823 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); in fdi_auto_training_started()
942 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
2348 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2349 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2350 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2351 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2352 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()