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Searched refs:EN0_ISR (Results 1 – 9 of 9) sorted by relevance

/drivers/net/ethernet/8390/
Dlib8390.c267 isr = ei_inb(e8390_base+EN0_ISR); in __ei_tx_timeout()
446 ei_inb_p(e8390_base + EN0_ISR), in __ei_interrupt()
455 ei_inb_p(e8390_base + EN0_ISR)); in __ei_interrupt()
458 while ((interrupts = ei_inb_p(e8390_base + EN0_ISR)) != 0 && in __ei_interrupt()
463 ei_outb_p(interrupts, e8390_base + EN0_ISR); in __ei_interrupt()
483 ei_outb_p(ENISR_COUNTERS, e8390_base + EN0_ISR); /* Ack intr. */ in __ei_interrupt()
488 ei_outb_p(ENISR_RDC, e8390_base + EN0_ISR); in __ei_interrupt()
500 ei_outb_p(ENISR_ALL, e8390_base + EN0_ISR); /* Ack. most intrs. */ in __ei_interrupt()
503 ei_outb_p(0xff, e8390_base + EN0_ISR); /* Ack. all intrs. */ in __ei_interrupt()
556 ei_outb_p(ENISR_TX_ERR, e8390_base + EN0_ISR); /* Ack intr. */ in ei_tx_err()
[all …]
Dne2k-pci.c302 while ((inb(ioaddr + EN0_ISR) & ENISR_RESET) == 0) in ne2k_pci_init_one()
310 outb(0xff, ioaddr + EN0_ISR); in ne2k_pci_init_one()
330 {0xFF, EN0_ISR}, in ne2k_pci_init_one()
486 while ((inb(NE_BASE+EN0_ISR) & ENISR_RESET) == 0) in ne2k_pci_reset_8390()
492 outb(ENISR_RESET, NE_BASE + EN0_ISR); in ne2k_pci_reset_8390()
530 outb(ENISR_RDC, nic_base + EN0_ISR); in ne2k_pci_get_8390_hdr()
583 outb(ENISR_RDC, nic_base + EN0_ISR); in ne2k_pci_block_input()
626 outb(ENISR_RDC, nic_base + EN0_ISR); in ne2k_pci_block_output()
651 while ((inb(nic_base + EN0_ISR) & ENISR_RDC) == 0) in ne2k_pci_block_output()
660 outb(ENISR_RDC, nic_base + EN0_ISR); in ne2k_pci_block_output()
Daxnet_cs.c202 {0xFF, EN0_ISR}, in get_prom()
479 outb_p(0xFF, nic_base + EN0_ISR); /* Clear bogus intr. */ in axnet_open()
531 if ((inb_p(nic_base+EN0_ISR) & ENISR_RESET) != 0) in axnet_reset_8390()
535 outb_p(ENISR_RESET, nic_base + EN0_ISR); /* Ack intr. */ in axnet_reset_8390()
563 if (info->stale++ && (inb_p(nic_base + EN0_ISR) & ENISR_ALL)) { in ei_watchdog()
920 isr = inb(e8390_base+EN0_ISR); in axnet_tx_timeout()
1116 inb_p(e8390_base + EN0_ISR), in ax_interrupt()
1124 inb_p(e8390_base + EN0_ISR)); in ax_interrupt()
1126 outb_p(0x00, e8390_base + EN0_ISR); in ax_interrupt()
1130 while ((interrupts = inb_p(e8390_base + EN0_ISR)) != 0 && in ax_interrupt()
[all …]
Dne.c348 while ((inb_p(ioaddr + EN0_ISR) & ENISR_RESET) == 0) in ne_probe1()
360 outb_p(0xff, ioaddr + EN0_ISR); /* Ack all intr. */ in ne_probe1()
375 {0xFF, EN0_ISR}, in ne_probe1()
560 while ((inb_p(NE_BASE+EN0_ISR) & ENISR_RESET) == 0) in ne_reset_8390()
565 outb_p(ENISR_RESET, NE_BASE + EN0_ISR); /* Ack intr. */ in ne_reset_8390()
599 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ne_get_8390_hdr()
673 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ne_block_input()
725 outb_p(ENISR_RDC, nic_base + EN0_ISR); in ne_block_output()
769 while ((inb_p(nic_base + EN0_ISR) & ENISR_RDC) == 0) in ne_block_output()
777 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ne_block_output()
Dax88796.c160 while ((ei_inb(addr + EN0_ISR) & ENISR_RESET) == 0) { in ax_reset_8390()
167 ei_outb(ENISR_RESET, addr + EN0_ISR); /* Ack intr. */ in ax_reset_8390()
216 ei_outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ax_get_8390_hdr()
295 ei_outb(ENISR_RDC, nic_base + EN0_ISR); in ax_block_output()
311 while ((ei_inb(nic_base + EN0_ISR) & ENISR_RDC) == 0) { in ax_block_output()
320 ei_outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ax_block_output()
713 ei_outb(ENISR_RDC, ioaddr + EN0_ISR); /* Ack intr. */ in ax_init_dev()
Dxsurf100.c212 ei_outb(ENISR_RDC, nic_base + EN0_ISR); in xs100_block_output()
226 while ((ei_inb(nic_base + EN0_ISR) & ENISR_RDC) == 0) { in xs100_block_output()
235 ei_outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in xs100_block_output()
Dpcnet_cs.c341 {0xFF, EN0_ISR}, in get_prom()
921 outb_p(0xFF, nic_base + EN0_ISR); /* Clear bogus intr. */ in pcnet_open()
974 if ((inb_p(nic_base+EN0_ISR) & ENISR_RESET) != 0) in pcnet_reset_8390()
978 outb_p(ENISR_RESET, nic_base + EN0_ISR); /* Ack intr. */ in pcnet_reset_8390()
1031 if (info->stale++ && (inb_p(nic_base + EN0_ISR) & ENISR_ALL)) { in ei_watchdog()
1159 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in dma_get_8390_hdr()
1216 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in dma_block_input()
1256 outb_p(ENISR_RDC, nic_base + EN0_ISR); in dma_block_output()
1292 while ((inb_p(nic_base + EN0_ISR) & ENISR_RDC) == 0) in dma_block_output()
1300 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in dma_block_output()
Detherh.c340 writeb (ENISR_RDC, addr + EN0_ISR); in etherh_block_output()
354 while ((readb (addr + EN0_ISR) & ENISR_RDC) == 0) in etherh_block_output()
362 writeb (ENISR_RDC, addr + EN0_ISR); in etherh_block_output()
403 writeb (ENISR_RDC, addr + EN0_ISR); in etherh_block_input()
440 writeb (ENISR_RDC, addr + EN0_ISR); in etherh_get_header()
D8390.h180 #define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */ macro