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Searched refs:FDI_RX_CTL (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_fdi.c59 cur_state = intel_de_read(dev_priv, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE; in assert_fdi_rx()
98 cur_state = intel_de_read(i915, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE; in assert_fdi_rx_pll()
294 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & in cpt_set_fdi_bc_bifurcation()
297 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) & in cpt_set_fdi_bc_bifurcation()
354 reg = FDI_RX_CTL(pipe); in intel_fdi_normal_train()
413 reg = FDI_RX_CTL(pipe); in ilk_fdi_link_train()
445 intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), in ilk_fdi_link_train()
447 intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe)); in ilk_fdi_link_train()
519 reg = FDI_RX_CTL(pipe); in gen6_fdi_link_train()
570 reg = FDI_RX_CTL(pipe); in gen6_fdi_link_train()
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Dintel_fdi_regs.h83 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) macro
Dintel_pch_display.c503 tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); in ilk_pch_get_config()
622 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); in lpt_pch_get_config()
Dintel_crt.c1118 FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c333 MMIO_D(FDI_RX_CTL(PIPE_A)); in iterate_generic_mmio()
334 MMIO_D(FDI_RX_CTL(PIPE_B)); in iterate_generic_mmio()
335 MMIO_D(FDI_RX_CTL(PIPE_C)); in iterate_generic_mmio()
/drivers/gpu/drm/i915/gvt/
Dhandlers.c845 fdi_rx_ctl = FDI_RX_CTL(pipe); in check_fdi_rx_train_status()
892 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
2315 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); in init_generic_mmio_info()
2316 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); in init_generic_mmio_info()
2317 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); in init_generic_mmio_info()