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Searched refs:FDI_TX_CTL (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_fdi.c37 cur_state = intel_de_read(dev_priv, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; in assert_fdi_tx()
88 cur_state = intel_de_read(i915, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE; in assert_fdi_tx_pll_enabled()
343 reg = FDI_TX_CTL(pipe); in intel_fdi_normal_train()
405 reg = FDI_TX_CTL(pipe); in ilk_fdi_link_train()
443 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), in ilk_fdi_link_train()
505 reg = FDI_TX_CTL(pipe); in gen6_fdi_link_train()
534 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), in gen6_fdi_link_train()
536 intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe)); in gen6_fdi_link_train()
559 reg = FDI_TX_CTL(pipe); in gen6_fdi_link_train()
585 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), in gen6_fdi_link_train()
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Dintel_fdi_regs.h33 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) macro
/drivers/gpu/drm/i915/gvt/
Dhandlers.c844 fdi_tx_ctl = FDI_TX_CTL(pipe); in check_fdi_rx_train_status()
895 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))