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Searched refs:FIFO (Results 1 – 25 of 34) sorted by relevance

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/drivers/staging/axis-fifo/
DKconfig3 # "Xilinx AXI-Stream FIFO IP core driver"
6 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.
10 The AXI Streaming FIFO allows memory mapped access to a AXI Streaming
11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
37 - xlnx,rx-fifo-depth: Depth of RX FIFO in words
45 - xlnx,tx-fifo-depth: Depth of TX FIFO in words
51 - xlnx,use-rx-data: <0x1> if RX FIFO is enabled, <0x0> otherwise
54 - xlnx,use-tx-data: <0x1> if TX FIFO is enabled, <0x0> otherwise
/drivers/video/fbdev/riva/
Driva_hw.c1351 LOAD_FIXED_STATE(nv4,FIFO); in UpdateFifoState()
1353 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); in UpdateFifoState()
1362 LOAD_FIXED_STATE(nv10,FIFO); in UpdateFifoState()
1364 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); in UpdateFifoState()
1397 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1436 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1441 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1482 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1487 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); in LoadStateExt()
1645 LOAD_FIXED_STATE(Riva,FIFO); in LoadStateExt()
[all …]
Dnv_driver.c332 par->riva.FIFO = in riva_common_setup()
Driva_hw.h454 volatile U032 __iomem *FIFO; member
/drivers/scsi/aic7xxx/
Daic79xx.seq169 * Since this status did not consume a FIFO, we have to
171 * to this transaction. There are two states that a FIFO still
174 * 1) Configured and draining to the host, with a FIFO handler.
177 * Case 1 can be detected by noticing a non-zero FIFO active
179 * the FIFO to complete the SCB.
182 * pointers for this same context in the other FIFO. So, if
308 * The FIFO use count field is shared with the
583 * Allocate a FIFO for a non-packetized transaction.
585 * can allocate a FIFO for a non-packetized transaction.
589 * Do whatever work is required to free a FIFO.
[all …]
Daic79xx.reg424 * Data FIFO Control
462 * Data FIFO Status
617 * Data FIFO Threshold
1136 * Data FIFO 0 PCI Status
1155 * Data FIFO 1 PCI Status
1692 * Data FIFO Status
2394 * Good Status FIFO
2405 * Data FIFO SCSI Transfer Control
2506 * Data FIFO Status
2516 field DLZERO 0x04 /* FIFO data ends on packet boundary. */
[all …]
Daic7xxx.seq1022 * true every time the PCI FIFO empties
1023 * regardless of the state of the SCSI FIFO.
1025 * SCSI FIFO to get data into the PCI FIFO
1043 * the data FIFO and acked them on the bus. The only
1046 * and then test to see if the data FIFO is non-empty.
1122 * the data FIFO should be flushed auto-magically on STCNT=0
1123 * or a phase change, so just wait for FIFO empty status.
1416 * On the 7895 the data FIFO will
1419 * the FIFO while it is enabled. So,
1777 * code do the rest. We also reset/reallocate the FIFO to make
[all …]
Daic7xxx.reg1029 * Queue In FIFO (p. 3-60)
1049 * Queue Out FIFO (p. 3-61)
1075 * Number of queued SCBs in the Out FIFO
/drivers/char/tpm/
DKconfig48 tristate "TPM Interface Specification 1.2 Interface / TPM 2.0 FIFO Interface"
53 TCG TIS 1.2 TPM specification (TPM1.2) or the TCG PTP FIFO
59 tristate "TPM Interface Specification 1.3 Interface / TPM 2.0 FIFO Interface - (SPI)"
65 TCG TIS 1.3 TPM specification (TPM1.2) or the TCG PTP FIFO
78 tristate "TPM Interface Specification 1.3 Interface / TPM 2.0 FIFO Interface - (I2C - generic)"
90 tristate "TPM Interface Specification 1.2 Interface / TPM 2.0 FIFO Interface (MMIO - SynQuacer)"
95 TCG TIS 1.2 TPM specification (TPM1.2) or the TCG PTP FIFO
/drivers/edac/
DKconfig434 bool "Altera Ethernet FIFO ECC"
438 Altera Ethernet FIFO Memory for Altera SoCs.
441 bool "Altera NAND FIFO ECC"
445 Altera NAND FIFO Memory for Altera SoCs.
448 bool "Altera DMA FIFO ECC"
452 Altera DMA FIFO Memory for Altera SoCs.
455 bool "Altera USB FIFO ECC"
459 Altera USB FIFO Memory for Altera SoCs.
462 bool "Altera QSPI FIFO ECC"
466 Altera QSPI FIFO Memory for Altera SoCs.
[all …]
/drivers/video/fbdev/nvidia/
Dnv_local.h92 NV_WR32(&(par)->FIFO[0x0010], 0, (data) << 2); \
96 #define READ_GET(par) (NV_RD32(&(par)->FIFO[0x0011], 0) >> 2)
Dnv_type.h166 volatile u32 __iomem *FIFO; member
Dnv_setup.c304 par->FIFO = par->REGS + (0x00800000 / 4); in NVCommonSetup()
/drivers/staging/media/omap4iss/
DTODO1 * Fix FIFO/buffer overflows and underflows
/drivers/parport/
DKconfig67 bool "Use FIFO/DMA if available"
73 As well as actually having a FIFO, or DMA capability, the kernel
76 FIFO. See <file:Documentation/admin-guide/parport.rst> to find out how to
Dparport_pc.c490 const unsigned long fifo = FIFO(port); in parport_pc_fifo_write_block_pio()
774 outb(0, FIFO(port)); in parport_pc_compat_write_block_pio()
869 outb(0, FIFO(port)); in parport_pc_ecp_write_block_pio()
1599 outb(0xaa, FIFO(pb)); in parport_ECP_supported()
1618 inb(FIFO(pb)); in parport_ECP_supported()
1642 outb(0xaa, FIFO(pb)); in parport_ECP_supported()
1887 outb(0xaa, FIFO(pb)); in irq_probe_ECP()
/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/
Dhost.fuc33 // HOST (R)FIFO packet format
62 // HOST->PWR comms - dequeue message(s) for process(es) from FIFO
/drivers/usb/musb/
DKconfig130 All data is copied between memory and FIFO by the CPU.
/drivers/net/ethernet/sis/
Dsis190.c208 FIFO = 0x00020000, enumerator
667 #define TxErrMask (WND | TABRT | FIFO | LINK) in sis190_tx_pkt_err()
676 if (status & FIFO) in sis190_tx_pkt_err()
/drivers/tty/
DKconfig348 to drain the FDC TX FIFO.
361 TX FIFO.
/drivers/tty/serial/
Dsifive.c129 #error Driver does not support configurations with different TX, RX FIFO sizes
/drivers/hwtracing/coresight/
DKconfig41 trace router - ETR) or sink (embedded trace FIFO). The driver
/drivers/i2c/busses/
DKconfig1155 tristate "UniPhier FIFO-less I2C controller"
1159 the UniPhier FIFO-less I2C interface embedded in PH1-LD4, PH1-sLD8,
1163 tristate "UniPhier FIFO-builtin I2C controller"
1167 the UniPhier FIFO-builtin I2C interface embedded in PH1-Pro4,
/drivers/scsi/
DFlashPoint.c492 #define FIFO BIT(4) macro
1739 if (hp_int & (FIFO | TIMEOUT | RESET | SCAM_SEL) || bm_status) { in FlashPoint_HandleInterrupt()
1744 (FIFO | TIMEOUT | RESET | SCAM_SEL)); in FlashPoint_HandleInterrupt()
2044 else if (p_int & FIFO) { in FPT_SccbMgr_bad_isr()
2046 WRW_HARPOON((p_port + hp_intstat), FIFO); in FPT_SccbMgr_bad_isr()

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