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Searched refs:F_PL_INTR_PCIX (Results 1 – 2 of 2) sorted by relevance

/drivers/net/ethernet/chelsio/cxgb/
Dsubr.c785 adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX; in t1_interrupts_enable()
786 pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX; in t1_interrupts_enable()
837 writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX, in t1_interrupts_clear()
864 if (cause & F_PL_INTR_PCIX) { in asic_slow_intr()
Dregs.h1779 #define F_PL_INTR_PCIX V_PL_INTR_PCIX(1U) macro