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Searched refs:GET_BITFIELD (Results 1 – 7 of 7) sorted by relevance

/drivers/edac/
Dskx_base.c174 return !!GET_BITFIELD(mcmtr, 2, 2); in skx_check_ecc()
221 #define SKX_SAD_MOD3MODE(sad) GET_BITFIELD((sad), 30, 31)
222 #define SKX_SAD_MOD3(sad) GET_BITFIELD((sad), 27, 27)
223 #define SKX_SAD_LIMIT(sad) (((u64)GET_BITFIELD((sad), 7, 26) << 26) | MASK26)
224 #define SKX_SAD_MOD3ASMOD2(sad) GET_BITFIELD((sad), 5, 6)
225 #define SKX_SAD_ATTR(sad) GET_BITFIELD((sad), 3, 4)
226 #define SKX_SAD_INTERLEAVE(sad) GET_BITFIELD((sad), 1, 2)
227 #define SKX_SAD_ENABLE(sad) GET_BITFIELD((sad), 0, 0)
300 idx = GET_BITFIELD(addr, 6, 8); in skx_sad_decode()
303 idx = GET_BITFIELD(addr, 8, 10); in skx_sad_decode()
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Dsb_edac.c51 #define GET_BITFIELD(v, lo, hi) \ macro
75 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
76 #define A7MODE(reg) GET_BITFIELD(reg, 26, 26)
146 return GET_BITFIELD(reg, table[interleave].start, in sad_pkg()
161 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
162 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
168 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
170 #define SOURCE_ID_KNL(reg) GET_BITFIELD(reg, 12, 14)
183 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
184 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
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Dskx_common.c210 *id = GET_BITFIELD(reg, 12, 14); in skx_get_src_id()
224 *id = GET_BITFIELD(reg, 0, 2); in skx_get_node_id()
231 switch (GET_BITFIELD(mtr, 8, 9)) { in get_width()
273 d->bus[0] = GET_BITFIELD(reg, 0, 7); in skx_get_all_bus_mappings()
274 d->bus[1] = GET_BITFIELD(reg, 8, 15); in skx_get_all_bus_mappings()
277 d->bus[2] = GET_BITFIELD(reg, 16, 23); in skx_get_all_bus_mappings()
278 d->bus[3] = GET_BITFIELD(reg, 24, 31); in skx_get_all_bus_mappings()
280 d->seg = GET_BITFIELD(reg, 16, 23); in skx_get_all_bus_mappings()
338 u32 val = GET_BITFIELD(reg, lobit, hibit); in skx_get_dimm_attr()
384 imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mcmtr, 0, 0); in skx_get_dimm_info()
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Digen6_edac.c42 #define GET_BITFIELD(v, lo, hi) (((v) & GENMASK_ULL(hi, lo)) >> (lo)) macro
82 #define ECC_ERROR_LOG_ADDR(v) GET_BITFIELD(v, 5, 38)
83 #define ECC_ERROR_LOG_SYND(v) GET_BITFIELD(v, 46, 61)
88 #define MCHBAR_BASE(v) (GET_BITFIELD(v, 16, 38) << 16)
94 #define MAD_INTER_CHANNEL_DDR_TYPE(v) GET_BITFIELD(v, 0, 2)
95 #define MAD_INTER_CHANNEL_ECHM(v) GET_BITFIELD(v, 3, 3)
96 #define MAD_INTER_CHANNEL_CH_L_MAP(v) GET_BITFIELD(v, 4, 4)
97 #define MAD_INTER_CHANNEL_CH_S_SIZE(v) ((u64)GET_BITFIELD(v, 12, 19) << 29)
101 #define MAD_INTRA_CH_DIMM_L_MAP(v) GET_BITFIELD(v, 0, 0)
105 #define MAD_DIMM_CH_DIMM_L_SIZE(v) ((u64)GET_BITFIELD(v, 0, 6) << 29)
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Di10nm_base.c61 #define I10NM_GET_SCK_MMIO_BASE(reg) (GET_BITFIELD(reg, 0, 28) << 23)
62 #define I10NM_GET_IMC_MMIO_OFFSET(reg) (GET_BITFIELD(reg, 0, 10) << 12)
63 #define I10NM_GET_IMC_MMIO_SIZE(reg) ((GET_BITFIELD(reg, 13, 23) - \
64 GET_BITFIELD(reg, 0, 10) + 1) << 12)
66 ((GET_BITFIELD(reg, 0, 10) << 12) + 0x140000)
71 #define I10NM_DDR_IMC_CH_CNT(reg) GET_BITFIELD(reg, 21, 24)
72 #define I10NM_IS_HBM_PRESENT(reg) GET_BITFIELD(reg, 27, 30)
73 #define I10NM_IS_HBM_IMC(reg) GET_BITFIELD(reg, 29, 29)
76 #define I10NM_SAD_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
77 #define I10NM_SAD_NM_CACHEABLE(reg) GET_BITFIELD(reg, 5, 5)
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Dskx_common.h29 #define GET_BITFIELD(v, lo, hi) \ macro
53 #define IS_DIMM_PRESENT(r) GET_BITFIELD(r, 15, 15)
54 #define IS_NVDIMM_PRESENT(r, i) GET_BITFIELD(r, i, i)
Dpnd2_edac.c125 #define GET_BITFIELD(v, lo, hi) (((v) & GENMASK_ULL(hi, lo)) >> (lo)) macro
1130 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); in pnd2_mce_output_error()
1131 u32 mscod = GET_BITFIELD(m->status, 16, 31); in pnd2_mce_output_error()
1132 u32 errcode = GET_BITFIELD(m->status, 0, 15); in pnd2_mce_output_error()
1133 u32 optypenum = GET_BITFIELD(m->status, 4, 6); in pnd2_mce_output_error()