Searched refs:HDMI_CON0 (Results 1 – 2 of 2) sorted by relevance
| /drivers/phy/mediatek/ |
| D | phy-mtk-hdmi-mt2701.c | 10 #define HDMI_CON0 0x00 macro
62 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); in mtk_hdmi_pll_prepare()
65 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); in mtk_hdmi_pll_prepare()
66 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); in mtk_hdmi_pll_prepare()
67 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); in mtk_hdmi_pll_prepare()
77 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); in mtk_hdmi_pll_unprepare()
78 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); in mtk_hdmi_pll_unprepare()
79 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); in mtk_hdmi_pll_unprepare()
82 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); in mtk_hdmi_pll_unprepare()
128 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_IMP_MASK); in mtk_hdmi_pll_set_rate()
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| D | phy-mtk-hdmi-mt8173.c | 10 #define HDMI_CON0 0x00 macro
93 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV); in mtk_hdmi_pll_prepare()
97 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN); in mtk_hdmi_pll_prepare()
113 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN); in mtk_hdmi_pll_unprepare()
116 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV); in mtk_hdmi_pll_unprepare()
160 mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_PLL_PREDIV, pre_div); in mtk_hdmi_pll_set_rate()
161 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV); in mtk_hdmi_pll_set_rate()
162 mtk_phy_update_bits(base + HDMI_CON0, in mtk_hdmi_pll_set_rate()
167 mtk_phy_update_bits(base + HDMI_CON0, in mtk_hdmi_pll_set_rate()
172 mtk_phy_update_bits(base + HDMI_CON0, in mtk_hdmi_pll_set_rate()
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