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Searched refs:HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID (Results 1 – 3 of 3) sorted by relevance

/drivers/staging/media/atomisp/pci/
Dirq_types_hrt.h55 hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID,
Dhive_isp_css_defs.h156 #define HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID 28 macro
/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
Dirq_local.h75 virq_sw_pin_0 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID,