1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2022 Intel Corporation */
3 #ifndef _ICP_QAT_HW_20_COMP_H_
4 #define _ICP_QAT_HW_20_COMP_H_
5
6 #include "icp_qat_hw_20_comp_defs.h"
7 #include "icp_qat_fw.h"
8
9 struct icp_qat_hw_comp_20_config_csr_lower {
10 enum icp_qat_hw_comp_20_extended_delay_match_mode edmm;
11 enum icp_qat_hw_comp_20_hw_comp_format algo;
12 enum icp_qat_hw_comp_20_search_depth sd;
13 enum icp_qat_hw_comp_20_hbs_control hbs;
14 enum icp_qat_hw_comp_20_abd abd;
15 enum icp_qat_hw_comp_20_lllbd_ctrl lllbd;
16 enum icp_qat_hw_comp_20_min_match_control mmctrl;
17 enum icp_qat_hw_comp_20_skip_hash_collision hash_col;
18 enum icp_qat_hw_comp_20_skip_hash_update hash_update;
19 enum icp_qat_hw_comp_20_byte_skip skip_ctrl;
20 };
21
22 static inline __u32
ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_comp_20_config_csr_lower csr)23 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_comp_20_config_csr_lower csr)
24 {
25 u32 val32 = 0;
26
27 QAT_FIELD_SET(val32, csr.algo,
28 ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS,
29 ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK);
30 QAT_FIELD_SET(val32, csr.sd,
31 ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS,
32 ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK);
33 QAT_FIELD_SET(val32, csr.edmm,
34 ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS,
35 ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK);
36 QAT_FIELD_SET(val32, csr.hbs,
37 ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,
38 ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK);
39 QAT_FIELD_SET(val32, csr.lllbd,
40 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS,
41 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK);
42 QAT_FIELD_SET(val32, csr.mmctrl,
43 ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,
44 ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);
45 QAT_FIELD_SET(val32, csr.hash_col,
46 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS,
47 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK);
48 QAT_FIELD_SET(val32, csr.hash_update,
49 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS,
50 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK);
51 QAT_FIELD_SET(val32, csr.skip_ctrl,
52 ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS,
53 ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK);
54 QAT_FIELD_SET(val32, csr.abd, ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS,
55 ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK);
56
57 return __builtin_bswap32(val32);
58 }
59
60 struct icp_qat_hw_comp_20_config_csr_upper {
61 enum icp_qat_hw_comp_20_scb_control scb_ctrl;
62 enum icp_qat_hw_comp_20_rmb_control rmb_ctrl;
63 enum icp_qat_hw_comp_20_som_control som_ctrl;
64 enum icp_qat_hw_comp_20_skip_hash_rd_control skip_hash_ctrl;
65 enum icp_qat_hw_comp_20_scb_unload_control scb_unload_ctrl;
66 enum icp_qat_hw_comp_20_disable_token_fusion_control disable_token_fusion_ctrl;
67 enum icp_qat_hw_comp_20_lbms lbms;
68 enum icp_qat_hw_comp_20_scb_mode_reset_mask scb_mode_reset;
69 __u16 lazy;
70 __u16 nice;
71 };
72
73 static inline __u32
ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(struct icp_qat_hw_comp_20_config_csr_upper csr)74 ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(struct icp_qat_hw_comp_20_config_csr_upper csr)
75 {
76 u32 val32 = 0;
77
78 QAT_FIELD_SET(val32, csr.scb_ctrl,
79 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS,
80 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK);
81 QAT_FIELD_SET(val32, csr.rmb_ctrl,
82 ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS,
83 ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK);
84 QAT_FIELD_SET(val32, csr.som_ctrl,
85 ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS,
86 ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK);
87 QAT_FIELD_SET(val32, csr.skip_hash_ctrl,
88 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS,
89 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK);
90 QAT_FIELD_SET(val32, csr.scb_unload_ctrl,
91 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS,
92 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK);
93 QAT_FIELD_SET(val32, csr.disable_token_fusion_ctrl,
94 ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS,
95 ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK);
96 QAT_FIELD_SET(val32, csr.lbms,
97 ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_BITPOS,
98 ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_MASK);
99 QAT_FIELD_SET(val32, csr.scb_mode_reset,
100 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS,
101 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK);
102 QAT_FIELD_SET(val32, csr.lazy,
103 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_BITPOS,
104 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_MASK);
105 QAT_FIELD_SET(val32, csr.nice,
106 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_BITPOS,
107 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_MASK);
108
109 return __builtin_bswap32(val32);
110 }
111
112 struct icp_qat_hw_decomp_20_config_csr_lower {
113 enum icp_qat_hw_decomp_20_hbs_control hbs;
114 enum icp_qat_hw_decomp_20_lbms lbms;
115 enum icp_qat_hw_decomp_20_hw_comp_format algo;
116 enum icp_qat_hw_decomp_20_min_match_control mmctrl;
117 enum icp_qat_hw_decomp_20_lz4_block_checksum_present lbc;
118 };
119
120 static inline __u32
ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_decomp_20_config_csr_lower csr)121 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_decomp_20_config_csr_lower csr)
122 {
123 u32 val32 = 0;
124
125 QAT_FIELD_SET(val32, csr.hbs,
126 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,
127 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_MASK);
128 QAT_FIELD_SET(val32, csr.lbms,
129 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_BITPOS,
130 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_MASK);
131 QAT_FIELD_SET(val32, csr.algo,
132 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_BITPOS,
133 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_MASK);
134 QAT_FIELD_SET(val32, csr.mmctrl,
135 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,
136 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);
137 QAT_FIELD_SET(val32, csr.lbc,
138 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_BITPOS,
139 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_MASK);
140
141 return __builtin_bswap32(val32);
142 }
143
144 struct icp_qat_hw_decomp_20_config_csr_upper {
145 enum icp_qat_hw_decomp_20_speculative_decoder_control sdc;
146 enum icp_qat_hw_decomp_20_mini_cam_control mcc;
147 };
148
149 static inline __u32
ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER(struct icp_qat_hw_decomp_20_config_csr_upper csr)150 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER(struct icp_qat_hw_decomp_20_config_csr_upper csr)
151 {
152 u32 val32 = 0;
153
154 QAT_FIELD_SET(val32, csr.sdc,
155 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_BITPOS,
156 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_MASK);
157 QAT_FIELD_SET(val32, csr.mcc,
158 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_BITPOS,
159 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_MASK);
160
161 return __builtin_bswap32(val32);
162 }
163
164 #endif
165