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Searched refs:IS_HASWELL (Results 1 – 25 of 45) sorted by relevance

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/drivers/gpu/drm/i915/soc/
Dintel_pch.c33 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
40 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
47 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
55 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
193 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) in intel_virt_detect_pch()
Dintel_dram.c704 if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9)) in intel_dram_edram_detect()
/drivers/gpu/drm/i915/display/
Dhsw_ips.c112 if (IS_HASWELL(i915) && in hsw_ips_need_disable()
153 if (IS_HASWELL(i915) && in hsw_ips_need_enable()
265 if (IS_HASWELL(i915)) { in hsw_ips_get_config()
Di9xx_plane.c115 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in i9xx_plane_has_fbc()
291 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { in i9xx_check_plane_surface()
304 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { in i9xx_check_plane_surface()
477 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { in i9xx_plane_update_arm()
841 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_primary_plane_create()
854 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_primary_plane_create()
1024 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { in i9xx_get_initial_plane_config()
Dintel_display_power.c1223 if (IS_HASWELL(dev_priv)) in assert_can_disable_lcpll()
1249 if (IS_HASWELL(dev_priv)) in hsw_read_dcomp()
1257 if (IS_HASWELL(dev_priv)) { in hsw_write_dcomp()
1937 } else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) { in intel_power_domains_init_hw()
2239 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { in intel_display_power_suspend_late()
2254 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { in intel_display_power_resume_early()
2271 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { in intel_display_power_suspend()
2295 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { in intel_display_power_resume()
Dintel_display.c810 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) in ilk_pfit_enable()
894 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); in needs_async_flip_vtd_wa()
1624 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { in hsw_crtc_enable()
2455 if (IS_HASWELL(dev_priv)) in intel_cpu_transcoder_has_m2_n2()
2566 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && in intel_set_transcoder_timings()
2597 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_pipe_is_interlaced()
3097 if (IS_HASWELL(dev_priv) && crtc_state->dither) in hsw_set_transconf()
3105 if (IS_HASWELL(dev_priv) && in hsw_set_transconf()
3262 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) in ilk_get_pfit_config()
3726 if (IS_HASWELL(dev_priv)) { in hsw_get_pipe_config()
[all …]
Dintel_sprite.c643 (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)); in ivb_need_sprite_gamma()
830 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { in ivb_sprite_update_arm()
1585 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { in intel_sprite_plane_create()
Dintel_pipe_crc.c308 if (IS_HASWELL(dev_priv) && in intel_crtc_crc_setup_workarounds()
Dintel_display_debugfs.c758 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { in i915_lpsp_status()
1181 else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) in i915_lpsp_capability_show()
Dintel_fbc.c935 } else if (DISPLAY_VER(i915) >= 8 || IS_HASWELL(i915)) { in intel_fbc_hw_tracking_covers_screen()
1160 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { in intel_fbc_check_plane()
Dintel_dp_aux.c751 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_dp_aux_init()
Dintel_cdclk.c2530 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_pixel_rate_to_cdclk()
3170 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_compute_max_dotclk()
3634 } else if (IS_HASWELL(dev_priv)) { in intel_init_cdclk_hooks()
Dintel_modeset_setup.c916 if (IS_HASWELL(i915)) in intel_early_display_was()
/drivers/gpu/drm/i915/
Di915_drv.h555 #define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL) macro
594 #define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
604 #define IS_HASWELL_GT3(i915) (IS_HASWELL(i915) && \
606 #define IS_HASWELL_GT1(i915) (IS_HASWELL(i915) && \
Di915_cmd_parser.c967 if (IS_HASWELL(engine->i915)) { in intel_engine_init_cmd_parser()
976 if (IS_HASWELL(engine->i915)) { in intel_engine_init_cmd_parser()
1000 } else if (IS_HASWELL(engine->i915)) { in intel_engine_init_cmd_parser()
1012 } else if (IS_HASWELL(engine->i915)) { in intel_engine_init_cmd_parser()
1559 if (IS_HASWELL(engine->i915)) in intel_engine_cmd_parser()
Dintel_device_info.c243 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) in intel_device_info_subplatform_init()
248 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { in intel_device_info_subplatform_init()
Dintel_clock_gating.c866 else if (IS_HASWELL(i915)) in intel_clock_gating_hooks_init()
/drivers/gpu/drm/i915/gt/
Dintel_llc.c91 } else if (IS_HASWELL(i915)) { in calc_ia_freq()
Dgen7_renderclear.c58 if (IS_HASWELL(i915)) { in batch_get_defaults()
391 IS_HASWELL(i915) ? in emit_batch()
Dintel_rps.c805 else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) in gen6_rps_set()
1184 if (IS_HASWELL(i915) || IS_BROADWELL(i915) || in gen6_rps_init()
2008 if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) { in intel_rps_init()
2085 else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) in intel_rps_get_cagf()
2278 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) in rps_frequency_dump()
Dintel_ring_submission.c696 IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0; in mi_set_context()
1188 if (IS_HASWELL(i915)) in setup_rcs()
Dgen6_ppgtt.c39 if (IS_HASWELL(i915)) { in gen7_ppgtt_enable()
Dintel_gt.c179 if (IS_HASWELL(i915)) in intel_gt_init_hw()
Dintel_sseu.c657 else if (IS_HASWELL(i915)) in intel_sseu_info_init()
/drivers/gpu/drm/i915/selftests/
Digt_spinner.c184 else if (IS_HASWELL(rq->i915)) in igt_spinner_create_request()

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