Home
last modified time | relevance | path

Searched refs:JH71X0__MUX (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/starfive/
Dclk-starfive-jh7100.c27 JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
32 JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
36 JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
41 JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
45 JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
48 JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
51 JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
55 JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
60 JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
64 JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
[all …]
Dclk-starfive-jh7110-sys.c39 JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
44 JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
50 JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
65 JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
99 JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
189 JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
273 JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2,
277 JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
288 JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
292 JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
[all …]
Dclk-starfive-jh7110-aon.c29 JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,
42 JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
51 JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
Dclk-starfive-jh71x0.h64 #define JH71X0__MUX(_idx, _name, _nparents, ...) \ macro
Dclk-starfive-jh7100-audio.c82 JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
Dclk-starfive-jh7110-isp.c56 JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2,