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Searched refs:L2 (Results 1 – 18 of 18) sorted by relevance

/drivers/net/ethernet/intel/iavf/
Diavf_common.c519 IAVF_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
520 IAVF_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
521 IAVF_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
524 IAVF_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
525 IAVF_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
528 IAVF_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
529 IAVF_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
530 IAVF_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
531 IAVF_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
532 IAVF_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
[all …]
/drivers/cache/
DKconfig5 bool "Andes Technology AX45MP L2 Cache controller"
9 Support for the L2 cache controller on Andes Technology AX45MP platforms.
/drivers/perf/
DKconfig139 bool "Qualcomm Technologies L2-cache PMU"
143 Provides support for the L2 cache performance monitor unit (PMU)
145 Adds the L2 cache PMU into the perf events subsystem for
146 monitoring L2 cache events.
/drivers/net/ethernet/atheros/
DKconfig30 tristate "Atheros L2 Fast Ethernet support"
35 This driver supports the Atheros L2 fast ethernet adapter.
/drivers/cpufreq/
Ds5pv210-cpufreq.c110 L0, L1, L2, L3, L4, enumerator
127 {0, L2, 400*1000},
153 [L2] = {
/drivers/edac/
DKconfig357 tristate "Highbank L2 Cache"
398 Coherent Processor Interconnect (CCPI) and L2 cache
419 bool "Altera L2 Cache ECC"
423 Altera L2 cache Memory for Altera SoCs. This option
424 requires L2 cache.
482 bool "Marvell Armada XP DDR and L2 Cache ECC"
486 DDR RAM and L2 cache controllers.
/drivers/net/ethernet/intel/ice/
Dice_lan_tx_rx.h700 ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
705 ICE_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
706 ICE_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
709 ICE_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
710 ICE_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
/drivers/soc/tegra/
DKconfig22 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
36 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
/drivers/memory/
DKconfig68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
74 possible to tune the L2 cache performance up by setting the data,
/drivers/net/ethernet/intel/i40e/
Di40e_common.c437 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
438 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
439 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
442 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
443 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
446 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
447 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
448 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
449 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
450 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
[all …]
/drivers/net/ethernet/wangxun/libwx/
Dwx_lib.c21 [0x11] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
22 [0x12] = WX_PTT(L2, NONE, NONE, NONE, TS, PAY2),
23 [0x13] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
24 [0x14] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
25 [0x15] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
26 [0x16] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
27 [0x17] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
30 [0x18 ... 0x1F] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
/drivers/pinctrl/aspeed/
Dpinctrl-aspeed-g4.c1483 #define L2 179 macro
1484 SIG_EXPR_LIST_DECL_SINGLE(L2, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
1485 SIG_EXPR_LIST_DECL_SINGLE(L2, ADC3, ADC3);
1486 PIN_DECL_(L2, SIG_EXPR_LIST_PTR(L2, GPIOW3), SIG_EXPR_LIST_PTR(L2, ADC3));
1487 FUNC_GROUP_DECL(ADC3, L2);
2050 ASPEED_PINCTRL_PIN(L2),
2498 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L2, L2, SCUA8, 7),
2499 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L2, L2, SCUA8, 7),
Dpinctrl-aspeed-g5.c605 #define L2 73 macro
606 SIG_EXPR_LIST_DECL_SINGLE(L2, SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
607 PIN_DECL_1(L2, GPIOJ1, SGPMLD);
617 FUNC_GROUP_DECL(SGPM, R2, L2, N3, N4);
2050 ASPEED_PINCTRL_PIN(L2),
/drivers/irqchip/
DKconfig121 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
129 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
136 tristate "Broadcom STB generic L2 interrupt controller driver"
/drivers/cpuidle/
DKconfig.arm131 CPU and L2 cores. It interface with various system drivers to put
/drivers/net/ethernet/mellanox/mlx5/core/
DKconfig74 Legacy SRIOV mode (L2 mac vlan steering based).
/drivers/soc/qcom/
DKconfig242 to manage cores, L2 low power modes and to configure the internal
/drivers/net/
DKconfig207 on packets. All interfaces (including the main interface) share L2
208 making it transparent to the connected L2 switch.