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Searched refs:LEVEL0_MPLL_FB_DIV (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/radeon/
Drv6xxd.h81 # define LEVEL0_MPLL_FB_DIV(x) ((x) << 8) macro
Drv6xx_dpm.c389 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider), in rv6xx_memory_clock_entry_set_feedback_divider()