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Searched refs:MACRO_TILE_ASPECT (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c86 #define MACRO_TILE_ASPECT(x) ((x) << 18) macro
411 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v6_0_tiling_mode_table_init()
419 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v6_0_tiling_mode_table_init()
427 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v6_0_tiling_mode_table_init()
434 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in gfx_v6_0_tiling_mode_table_init()
446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in gfx_v6_0_tiling_mode_table_init()
454 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in gfx_v6_0_tiling_mode_table_init()
462 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in gfx_v6_0_tiling_mode_table_init()
474 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v6_0_tiling_mode_table_init()
482 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v6_0_tiling_mode_table_init()
[all …]
Dgfx_v8_0.c75 #define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT) macro
2197 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()
2201 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()
2205 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()
2209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v8_0_tiling_mode_table_init()
2213 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()
2217 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()
2221 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()
2225 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v8_0_tiling_mode_table_init()
2229 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v8_0_tiling_mode_table_init()
[all …]
Dgfx_v7_0.c1124 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v7_0_tiling_mode_table_init()
1128 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v7_0_tiling_mode_table_init()
1132 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v7_0_tiling_mode_table_init()
1136 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v7_0_tiling_mode_table_init()
1140 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v7_0_tiling_mode_table_init()
1144 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v7_0_tiling_mode_table_init()
1148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in gfx_v7_0_tiling_mode_table_init()
1152 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v7_0_tiling_mode_table_init()
1156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v7_0_tiling_mode_table_init()
1160 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v7_0_tiling_mode_table_init()
[all …]
Dcikd.h196 # define MACRO_TILE_ASPECT(x) ((x) << 4) macro
Dsid.h1213 # define MACRO_TILE_ASPECT(x) ((x) << 18) macro
Ddce_v8_0.c1912 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base()
Ddce_v6_0.c1943 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base()
Ddce_v10_0.c1987 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base()
Ddce_v11_0.c2037 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base()
/drivers/gpu/drm/radeon/
Dsi.c2522 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()
2531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()
2540 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()
2549 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()
2558 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()
2567 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()
2576 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); in si_tiling_mode_table_init()
2585 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()
2594 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()
2603 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()
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Dcik.c2438 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in cik_tiling_mode_table_init()
2442 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in cik_tiling_mode_table_init()
2446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in cik_tiling_mode_table_init()
2450 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in cik_tiling_mode_table_init()
2454 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in cik_tiling_mode_table_init()
2458 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in cik_tiling_mode_table_init()
2462 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in cik_tiling_mode_table_init()
2466 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in cik_tiling_mode_table_init()
2470 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in cik_tiling_mode_table_init()
2474 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in cik_tiling_mode_table_init()
[all …]
Dsid.h1216 # define MACRO_TILE_ASPECT(x) ((x) << 18) macro
Dcikd.h1270 # define MACRO_TILE_ASPECT(x) ((x) << 4) macro
Devergreend.h2416 # define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) macro
Devergreen_cs.c2372 MACRO_TILE_ASPECT(mtaspect) | in evergreen_packet3_check()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_plane.c189 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in fill_gfx8_tiling_info_from_flags()
/drivers/gpu/drm/amd/include/
Dnavi10_enum.h1766 typedef enum MACRO_TILE_ASPECT { enum
1771 } MACRO_TILE_ASPECT; typedef