1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * MGA Millennium (MGA2064W) functions 4 * MGA Mystique (MGA1064SG) functions 5 * 6 * Copyright 1996 The XFree86 Project, Inc. 7 * 8 * Authors 9 * Dirk Hohndel 10 * hohndel@XFree86.Org 11 * David Dawes 12 * dawes@XFree86.Org 13 * Contributors: 14 * Guy DESBIEF, Aix-en-provence, France 15 * g.desbief@aix.pacwan.net 16 * MGA1064SG Mystique register file 17 */ 18 19 #ifndef _MGA_REG_H_ 20 #define _MGA_REG_H_ 21 22 #include <linux/bits.h> 23 24 #define MGAREG_DWGCTL 0x1c00 25 #define MGAREG_MACCESS 0x1c04 26 /* the following is a mystique only register */ 27 #define MGAREG_MCTLWTST 0x1c08 28 #define MGAREG_ZORG 0x1c0c 29 30 #define MGAREG_PAT0 0x1c10 31 #define MGAREG_PAT1 0x1c14 32 #define MGAREG_PLNWT 0x1c1c 33 34 #define MGAREG_BCOL 0x1c20 35 #define MGAREG_FCOL 0x1c24 36 37 #define MGAREG_SRC0 0x1c30 38 #define MGAREG_SRC1 0x1c34 39 #define MGAREG_SRC2 0x1c38 40 #define MGAREG_SRC3 0x1c3c 41 42 #define MGAREG_XYSTRT 0x1c40 43 #define MGAREG_XYEND 0x1c44 44 45 #define MGAREG_SHIFT 0x1c50 46 /* the following is a mystique only register */ 47 #define MGAREG_DMAPAD 0x1c54 48 #define MGAREG_SGN 0x1c58 49 #define MGAREG_LEN 0x1c5c 50 51 #define MGAREG_AR0 0x1c60 52 #define MGAREG_AR1 0x1c64 53 #define MGAREG_AR2 0x1c68 54 #define MGAREG_AR3 0x1c6c 55 #define MGAREG_AR4 0x1c70 56 #define MGAREG_AR5 0x1c74 57 #define MGAREG_AR6 0x1c78 58 59 #define MGAREG_CXBNDRY 0x1c80 60 #define MGAREG_FXBNDRY 0x1c84 61 #define MGAREG_YDSTLEN 0x1c88 62 #define MGAREG_PITCH 0x1c8c 63 64 #define MGAREG_YDST 0x1c90 65 #define MGAREG_YDSTORG 0x1c94 66 #define MGAREG_YTOP 0x1c98 67 #define MGAREG_YBOT 0x1c9c 68 69 #define MGAREG_CXLEFT 0x1ca0 70 #define MGAREG_CXRIGHT 0x1ca4 71 #define MGAREG_FXLEFT 0x1ca8 72 #define MGAREG_FXRIGHT 0x1cac 73 74 #define MGAREG_XDST 0x1cb0 75 76 #define MGAREG_DR0 0x1cc0 77 #define MGAREG_DR1 0x1cc4 78 #define MGAREG_DR2 0x1cc8 79 #define MGAREG_DR3 0x1ccc 80 81 #define MGAREG_DR4 0x1cd0 82 #define MGAREG_DR5 0x1cd4 83 #define MGAREG_DR6 0x1cd8 84 #define MGAREG_DR7 0x1cdc 85 86 #define MGAREG_DR8 0x1ce0 87 #define MGAREG_DR9 0x1ce4 88 #define MGAREG_DR10 0x1ce8 89 #define MGAREG_DR11 0x1cec 90 91 #define MGAREG_DR12 0x1cf0 92 #define MGAREG_DR13 0x1cf4 93 #define MGAREG_DR14 0x1cf8 94 #define MGAREG_DR15 0x1cfc 95 96 #define MGAREG_SRCORG 0x2cb4 97 #define MGAREG_DSTORG 0x2cb8 98 99 /* add or this to one of the previous "power registers" to start 100 the drawing engine */ 101 102 #define MGAREG_EXEC 0x0100 103 104 #define MGAREG_FIFOSTATUS 0x1e10 105 #define MGAREG_Status 0x1e14 106 #define MGAREG_CACHEFLUSH 0x1fff 107 #define MGAREG_ICLEAR 0x1e18 108 #define MGAREG_IEN 0x1e1c 109 110 #define MGAREG_VCOUNT 0x1e20 111 112 #define MGAREG_Reset 0x1e40 113 114 #define MGAREG_OPMODE 0x1e54 115 116 /* Warp Registers */ 117 #define MGAREG_WIADDR 0x1dc0 118 #define MGAREG_WIADDR2 0x1dd8 119 #define MGAREG_WGETMSB 0x1dc8 120 #define MGAREG_WVRTXSZ 0x1dcc 121 #define MGAREG_WACCEPTSEQ 0x1dd4 122 #define MGAREG_WMISC 0x1e70 123 124 #define MGAREG_MEMCTL 0x2e08 125 126 /* OPMODE register additives */ 127 128 #define MGAOPM_DMA_GENERAL (0x00 << 2) 129 #define MGAOPM_DMA_BLIT (0x01 << 2) 130 #define MGAOPM_DMA_VECTOR (0x10 << 2) 131 132 /* MACCESS register additives */ 133 #define MGAMAC_PW8 0x00 134 #define MGAMAC_PW16 0x01 135 #define MGAMAC_PW24 0x03 /* not a typo */ 136 #define MGAMAC_PW32 0x02 /* not a typo */ 137 #define MGAMAC_BYPASS332 0x10000000 138 #define MGAMAC_NODITHER 0x40000000 139 #define MGAMAC_DIT555 0x80000000 140 141 /* DWGCTL register additives */ 142 143 /* Lines */ 144 145 #define MGADWG_LINE_OPEN 0x00 146 #define MGADWG_AUTOLINE_OPEN 0x01 147 #define MGADWG_LINE_CLOSE 0x02 148 #define MGADWG_AUTOLINE_CLOSE 0x03 149 150 /* Trapezoids */ 151 #define MGADWG_TRAP 0x04 152 #define MGADWG_TEXTURE_TRAP 0x06 153 154 /* BitBlts */ 155 156 #define MGADWG_BITBLT 0x08 157 #define MGADWG_FBITBLT 0x0c 158 #define MGADWG_ILOAD 0x09 159 #define MGADWG_ILOAD_SCALE 0x0d 160 #define MGADWG_ILOAD_FILTER 0x0f 161 #define MGADWG_ILOAD_HIQH 0x07 162 #define MGADWG_ILOAD_HIQHV 0x0e 163 #define MGADWG_IDUMP 0x0a 164 165 /* atype access to WRAM */ 166 167 #define MGADWG_RPL ( 0x00 << 4 ) 168 #define MGADWG_RSTR ( 0x01 << 4 ) 169 #define MGADWG_ZI ( 0x03 << 4 ) 170 #define MGADWG_BLK ( 0x04 << 4 ) 171 #define MGADWG_I ( 0x07 << 4 ) 172 173 /* specifies whether bit blits are linear or xy */ 174 #define MGADWG_LINEAR ( 0x01 << 7 ) 175 176 /* z drawing mode. use MGADWG_NOZCMP for always */ 177 178 #define MGADWG_NOZCMP ( 0x00 << 8 ) 179 #define MGADWG_ZE ( 0x02 << 8 ) 180 #define MGADWG_ZNE ( 0x03 << 8 ) 181 #define MGADWG_ZLT ( 0x04 << 8 ) 182 #define MGADWG_ZLTE ( 0x05 << 8 ) 183 #define MGADWG_GT ( 0x06 << 8 ) 184 #define MGADWG_GTE ( 0x07 << 8 ) 185 186 /* use this to force colour expansion circuitry to do its stuff */ 187 188 #define MGADWG_SOLID ( 0x01 << 11 ) 189 190 /* ar register at zero */ 191 192 #define MGADWG_ARZERO ( 0x01 << 12 ) 193 194 #define MGADWG_SGNZERO ( 0x01 << 13 ) 195 196 #define MGADWG_SHIFTZERO ( 0x01 << 14 ) 197 198 /* See table on 4-43 for bop ALU operations */ 199 200 /* See table on 4-44 for translucidity masks */ 201 202 #define MGADWG_BMONOLEF ( 0x00 << 25 ) 203 #define MGADWG_BMONOWF ( 0x04 << 25 ) 204 #define MGADWG_BPLAN ( 0x01 << 25 ) 205 206 /* note that if bfcol is specified and you're doing a bitblt, it causes 207 a fbitblt to be performed, so check that you obey the fbitblt rules */ 208 209 #define MGADWG_BFCOL ( 0x02 << 25 ) 210 #define MGADWG_BUYUV ( 0x0e << 25 ) 211 #define MGADWG_BU32BGR ( 0x03 << 25 ) 212 #define MGADWG_BU32RGB ( 0x07 << 25 ) 213 #define MGADWG_BU24BGR ( 0x0b << 25 ) 214 #define MGADWG_BU24RGB ( 0x0f << 25 ) 215 216 #define MGADWG_PATTERN ( 0x01 << 29 ) 217 #define MGADWG_TRANSC ( 0x01 << 30 ) 218 #define MGAREG_MISC_WRITE 0x3c2 219 #define MGAREG_MISC_READ 0x3cc 220 #define MGAREG_MEM_MISC_WRITE 0x1fc2 221 #define MGAREG_MEM_MISC_READ 0x1fcc 222 223 #define MGAREG_MISC_IOADSEL (0x1 << 0) 224 #define MGAREG_MISC_RAMMAPEN (0x1 << 1) 225 #define MGAREG_MISC_CLKSEL_MASK GENMASK(3, 2) 226 #define MGAREG_MISC_CLKSEL_VGA25 (0x0 << 2) 227 #define MGAREG_MISC_CLKSEL_VGA28 (0x1 << 2) 228 #define MGAREG_MISC_CLKSEL_MGA (0x3 << 2) 229 #define MGAREG_MISC_VIDEO_DIS (0x1 << 4) 230 #define MGAREG_MISC_HIGH_PG_SEL (0x1 << 5) 231 #define MGAREG_MISC_HSYNCPOL BIT(6) 232 #define MGAREG_MISC_VSYNCPOL BIT(7) 233 234 /* MMIO VGA registers */ 235 #define MGAREG_SEQ_INDEX 0x1fc4 236 #define MGAREG_SEQ_DATA 0x1fc5 237 238 #define MGAREG_SEQ0_ASYNCRST BIT(0) 239 #define MGAREG_SEQ0_SYNCRST BIT(1) 240 241 #define MGAREG_SEQ1_SCROFF BIT(5) 242 243 #define MGAREG_CRTC_INDEX 0x1fd4 244 #define MGAREG_CRTC_DATA 0x1fd5 245 246 #define MGAREG_CRTC11_VINTCLR BIT(4) 247 #define MGAREG_CRTC11_VINTEN BIT(5) 248 #define MGAREG_CRTC11_CRTCPROTECT BIT(7) 249 250 #define MGAREG_CRTCEXT_INDEX 0x1fde 251 #define MGAREG_CRTCEXT_DATA 0x1fdf 252 253 #define MGAREG_CRTCEXT0_OFFSET_MASK GENMASK(5, 4) 254 255 #define MGAREG_CRTCEXT1_VRSTEN BIT(7) 256 #define MGAREG_CRTCEXT1_VSYNCOFF BIT(5) 257 #define MGAREG_CRTCEXT1_HSYNCOFF BIT(4) 258 #define MGAREG_CRTCEXT1_HRSTEN BIT(3) 259 260 #define MGAREG_CRTCEXT3_MGAMODE BIT(7) 261 262 /* Cursor X and Y position */ 263 #define MGA_CURPOSXL 0x3c0c 264 #define MGA_CURPOSXH 0x3c0d 265 #define MGA_CURPOSYL 0x3c0e 266 #define MGA_CURPOSYH 0x3c0f 267 268 /* MGA bits for registers PCI_OPTION_REG */ 269 #define MGA1064_OPT_SYS_CLK_PCI ( 0x00 << 0 ) 270 #define MGA1064_OPT_SYS_CLK_PLL ( 0x01 << 0 ) 271 #define MGA1064_OPT_SYS_CLK_EXT ( 0x02 << 0 ) 272 #define MGA1064_OPT_SYS_CLK_MSK ( 0x03 << 0 ) 273 274 #define MGA1064_OPT_SYS_CLK_DIS ( 0x01 << 2 ) 275 #define MGA1064_OPT_G_CLK_DIV_1 ( 0x01 << 3 ) 276 #define MGA1064_OPT_M_CLK_DIV_1 ( 0x01 << 4 ) 277 278 #define MGA1064_OPT_SYS_PLL_PDN ( 0x01 << 5 ) 279 #define MGA1064_OPT_VGA_ION ( 0x01 << 8 ) 280 281 /* MGA registers in PCI config space */ 282 #define PCI_MGA_INDEX 0x44 283 #define PCI_MGA_DATA 0x48 284 #define PCI_MGA_OPTION 0x40 285 #define PCI_MGA_OPTION2 0x50 286 #define PCI_MGA_OPTION3 0x54 287 288 #define PCI_MGA_OPTION_HARDPWMSK BIT(14) 289 290 #define RAMDAC_OFFSET 0x3c00 291 292 /* TVP3026 direct registers */ 293 294 #define TVP3026_INDEX 0x00 295 #define TVP3026_WADR_PAL 0x00 296 #define TVP3026_COL_PAL 0x01 297 #define TVP3026_PIX_RD_MSK 0x02 298 #define TVP3026_RADR_PAL 0x03 299 #define TVP3026_CUR_COL_ADDR 0x04 300 #define TVP3026_CUR_COL_DATA 0x05 301 #define TVP3026_DATA 0x0a 302 #define TVP3026_CUR_RAM 0x0b 303 #define TVP3026_CUR_XLOW 0x0c 304 #define TVP3026_CUR_XHI 0x0d 305 #define TVP3026_CUR_YLOW 0x0e 306 #define TVP3026_CUR_YHI 0x0f 307 308 /* TVP3026 indirect registers */ 309 310 #define TVP3026_SILICON_REV 0x01 311 #define TVP3026_CURSOR_CTL 0x06 312 #define TVP3026_LATCH_CTL 0x0f 313 #define TVP3026_TRUE_COLOR_CTL 0x18 314 #define TVP3026_MUX_CTL 0x19 315 #define TVP3026_CLK_SEL 0x1a 316 #define TVP3026_PAL_PAGE 0x1c 317 #define TVP3026_GEN_CTL 0x1d 318 #define TVP3026_MISC_CTL 0x1e 319 #define TVP3026_GEN_IO_CTL 0x2a 320 #define TVP3026_GEN_IO_DATA 0x2b 321 #define TVP3026_PLL_ADDR 0x2c 322 #define TVP3026_PIX_CLK_DATA 0x2d 323 #define TVP3026_MEM_CLK_DATA 0x2e 324 #define TVP3026_LOAD_CLK_DATA 0x2f 325 #define TVP3026_KEY_RED_LOW 0x32 326 #define TVP3026_KEY_RED_HI 0x33 327 #define TVP3026_KEY_GREEN_LOW 0x34 328 #define TVP3026_KEY_GREEN_HI 0x35 329 #define TVP3026_KEY_BLUE_LOW 0x36 330 #define TVP3026_KEY_BLUE_HI 0x37 331 #define TVP3026_KEY_CTL 0x38 332 #define TVP3026_MCLK_CTL 0x39 333 #define TVP3026_SENSE_TEST 0x3a 334 #define TVP3026_TEST_DATA 0x3b 335 #define TVP3026_CRC_LSB 0x3c 336 #define TVP3026_CRC_MSB 0x3d 337 #define TVP3026_CRC_CTL 0x3e 338 #define TVP3026_ID 0x3f 339 #define TVP3026_RESET 0xff 340 341 342 /* MGA1064 DAC Register file */ 343 /* MGA1064 direct registers */ 344 345 #define MGA1064_INDEX 0x00 346 #define MGA1064_WADR_PAL 0x00 347 #define MGA1064_SPAREREG 0x00 348 #define MGA1064_COL_PAL 0x01 349 #define MGA1064_PIX_RD_MSK 0x02 350 #define MGA1064_RADR_PAL 0x03 351 #define MGA1064_DATA 0x0a 352 353 #define MGA1064_CUR_XLOW 0x0c 354 #define MGA1064_CUR_XHI 0x0d 355 #define MGA1064_CUR_YLOW 0x0e 356 #define MGA1064_CUR_YHI 0x0f 357 358 /* MGA1064 indirect registers */ 359 #define MGA1064_DVI_PIPE_CTL 0x03 360 #define MGA1064_CURSOR_BASE_ADR_LOW 0x04 361 #define MGA1064_CURSOR_BASE_ADR_HI 0x05 362 #define MGA1064_CURSOR_CTL 0x06 363 #define MGA1064_CURSOR_COL0_RED 0x08 364 #define MGA1064_CURSOR_COL0_GREEN 0x09 365 #define MGA1064_CURSOR_COL0_BLUE 0x0a 366 367 #define MGA1064_CURSOR_COL1_RED 0x0c 368 #define MGA1064_CURSOR_COL1_GREEN 0x0d 369 #define MGA1064_CURSOR_COL1_BLUE 0x0e 370 371 #define MGA1064_CURSOR_COL2_RED 0x010 372 #define MGA1064_CURSOR_COL2_GREEN 0x011 373 #define MGA1064_CURSOR_COL2_BLUE 0x012 374 375 #define MGA1064_VREF_CTL 0x018 376 377 #define MGA1064_MUL_CTL 0x19 378 #define MGA1064_MUL_CTL_8bits 0x0 379 #define MGA1064_MUL_CTL_15bits 0x01 380 #define MGA1064_MUL_CTL_16bits 0x02 381 #define MGA1064_MUL_CTL_24bits 0x03 382 #define MGA1064_MUL_CTL_32bits 0x04 383 #define MGA1064_MUL_CTL_2G8V16bits 0x05 384 #define MGA1064_MUL_CTL_G16V16bits 0x06 385 #define MGA1064_MUL_CTL_32_24bits 0x07 386 387 #define MGA1064_PIX_CLK_CTL 0x1a 388 #define MGA1064_PIX_CLK_CTL_CLK_DIS ( 0x01 << 2 ) 389 #define MGA1064_PIX_CLK_CTL_CLK_POW_DOWN ( 0x01 << 3 ) 390 #define MGA1064_PIX_CLK_CTL_SEL_PCI ( 0x00 << 0 ) 391 #define MGA1064_PIX_CLK_CTL_SEL_PLL ( 0x01 << 0 ) 392 #define MGA1064_PIX_CLK_CTL_SEL_EXT ( 0x02 << 0 ) 393 #define MGA1064_PIX_CLK_CTL_SEL_MSK ( 0x03 << 0 ) 394 395 #define MGA1064_GEN_CTL 0x1d 396 #define MGA1064_GEN_CTL_SYNC_ON_GREEN_DIS (0x01 << 5) 397 #define MGA1064_MISC_CTL 0x1e 398 #define MGA1064_MISC_CTL_DAC_EN ( 0x01 << 0 ) 399 #define MGA1064_MISC_CTL_VGA ( 0x01 << 1 ) 400 #define MGA1064_MISC_CTL_DIS_CON ( 0x03 << 1 ) 401 #define MGA1064_MISC_CTL_MAFC ( 0x02 << 1 ) 402 #define MGA1064_MISC_CTL_VGA8 ( 0x01 << 3 ) 403 #define MGA1064_MISC_CTL_DAC_RAM_CS ( 0x01 << 4 ) 404 405 #define MGA1064_GEN_IO_CTL2 0x29 406 #define MGA1064_GEN_IO_CTL 0x2a 407 #define MGA1064_GEN_IO_DATA 0x2b 408 #define MGA1064_SYS_PLL_M 0x2c 409 #define MGA1064_SYS_PLL_N 0x2d 410 #define MGA1064_SYS_PLL_P 0x2e 411 #define MGA1064_SYS_PLL_STAT 0x2f 412 413 #define MGA1064_REMHEADCTL 0x30 414 #define MGA1064_REMHEADCTL_CLKDIS ( 0x01 << 0 ) 415 #define MGA1064_REMHEADCTL_CLKSL_OFF ( 0x00 << 1 ) 416 #define MGA1064_REMHEADCTL_CLKSL_PLL ( 0x01 << 1 ) 417 #define MGA1064_REMHEADCTL_CLKSL_PCI ( 0x02 << 1 ) 418 #define MGA1064_REMHEADCTL_CLKSL_MSK ( 0x03 << 1 ) 419 420 #define MGA1064_REMHEADCTL2 0x31 421 422 #define MGA1064_ZOOM_CTL 0x38 423 #define MGA1064_SENSE_TST 0x3a 424 425 #define MGA1064_CRC_LSB 0x3c 426 #define MGA1064_CRC_MSB 0x3d 427 #define MGA1064_CRC_CTL 0x3e 428 #define MGA1064_COL_KEY_MSK_LSB 0x40 429 #define MGA1064_COL_KEY_MSK_MSB 0x41 430 #define MGA1064_COL_KEY_LSB 0x42 431 #define MGA1064_COL_KEY_MSB 0x43 432 #define MGA1064_PIX_PLLA_M 0x44 433 #define MGA1064_PIX_PLLA_N 0x45 434 #define MGA1064_PIX_PLLA_P 0x46 435 #define MGA1064_PIX_PLLB_M 0x48 436 #define MGA1064_PIX_PLLB_N 0x49 437 #define MGA1064_PIX_PLLB_P 0x4a 438 #define MGA1064_PIX_PLLC_M 0x4c 439 #define MGA1064_PIX_PLLC_N 0x4d 440 #define MGA1064_PIX_PLLC_P 0x4e 441 442 #define MGA1064_PIX_PLL_STAT 0x4f 443 444 /*Added for G450 dual head*/ 445 446 #define MGA1064_VID_PLL_STAT 0x8c 447 #define MGA1064_VID_PLL_P 0x8D 448 #define MGA1064_VID_PLL_M 0x8E 449 #define MGA1064_VID_PLL_N 0x8F 450 451 /* Modified PLL for G200 Winbond (G200WB) */ 452 #define MGA1064_WB_PIX_PLLC_M 0xb7 453 #define MGA1064_WB_PIX_PLLC_N 0xb6 454 #define MGA1064_WB_PIX_PLLC_P 0xb8 455 456 /* Modified PLL for G200 Maxim (G200EV) */ 457 #define MGA1064_EV_PIX_PLLC_M 0xb6 458 #define MGA1064_EV_PIX_PLLC_N 0xb7 459 #define MGA1064_EV_PIX_PLLC_P 0xb8 460 461 /* Modified PLL for G200 EH */ 462 #define MGA1064_EH_PIX_PLLC_M 0xb6 463 #define MGA1064_EH_PIX_PLLC_N 0xb7 464 #define MGA1064_EH_PIX_PLLC_P 0xb8 465 466 /* Modified PLL for G200 Maxim (G200ER) */ 467 #define MGA1064_ER_PIX_PLLC_M 0xb7 468 #define MGA1064_ER_PIX_PLLC_N 0xb6 469 #define MGA1064_ER_PIX_PLLC_P 0xb8 470 471 #define MGA1064_DISP_CTL 0x8a 472 #define MGA1064_DISP_CTL_DAC1OUTSEL_MASK 0x01 473 #define MGA1064_DISP_CTL_DAC1OUTSEL_DIS 0x00 474 #define MGA1064_DISP_CTL_DAC1OUTSEL_EN 0x01 475 #define MGA1064_DISP_CTL_DAC2OUTSEL_MASK (0x03 << 2) 476 #define MGA1064_DISP_CTL_DAC2OUTSEL_DIS 0x00 477 #define MGA1064_DISP_CTL_DAC2OUTSEL_CRTC1 (0x01 << 2) 478 #define MGA1064_DISP_CTL_DAC2OUTSEL_CRTC2 (0x02 << 2) 479 #define MGA1064_DISP_CTL_DAC2OUTSEL_TVE (0x03 << 2) 480 #define MGA1064_DISP_CTL_PANOUTSEL_MASK (0x03 << 5) 481 #define MGA1064_DISP_CTL_PANOUTSEL_DIS 0x00 482 #define MGA1064_DISP_CTL_PANOUTSEL_CRTC1 (0x01 << 5) 483 #define MGA1064_DISP_CTL_PANOUTSEL_CRTC2RGB (0x02 << 5) 484 #define MGA1064_DISP_CTL_PANOUTSEL_CRTC2656 (0x03 << 5) 485 486 #define MGA1064_SYNC_CTL 0x8b 487 488 #define MGA1064_PWR_CTL 0xa0 489 #define MGA1064_PWR_CTL_DAC2_EN (0x01 << 0) 490 #define MGA1064_PWR_CTL_VID_PLL_EN (0x01 << 1) 491 #define MGA1064_PWR_CTL_PANEL_EN (0x01 << 2) 492 #define MGA1064_PWR_CTL_RFIFO_EN (0x01 << 3) 493 #define MGA1064_PWR_CTL_CFIFO_EN (0x01 << 4) 494 495 #define MGA1064_PAN_CTL 0xa2 496 497 /* Using crtc2 */ 498 #define MGAREG2_C2CTL 0x10 499 #define MGAREG2_C2HPARAM 0x14 500 #define MGAREG2_C2HSYNC 0x18 501 #define MGAREG2_C2VPARAM 0x1c 502 #define MGAREG2_C2VSYNC 0x20 503 #define MGAREG2_C2STARTADD0 0x28 504 505 #define MGAREG2_C2OFFSET 0x40 506 #define MGAREG2_C2DATACTL 0x4c 507 508 #define MGAREG_C2CTL 0x3c10 509 #define MGAREG_C2CTL_C2_EN 0x01 510 511 #define MGAREG_C2_HIPRILVL_M (0x07 << 4) 512 #define MGAREG_C2_MAXHIPRI_M (0x07 << 8) 513 514 #define MGAREG_C2CTL_PIXCLKSEL_MASK (0x03 << 1) 515 #define MGAREG_C2CTL_PIXCLKSELH_MASK (0x01 << 14) 516 #define MGAREG_C2CTL_PIXCLKSEL_PCICLK 0x00 517 #define MGAREG_C2CTL_PIXCLKSEL_VDOCLK (0x01 << 1) 518 #define MGAREG_C2CTL_PIXCLKSEL_PIXELPLL (0x02 << 1) 519 #define MGAREG_C2CTL_PIXCLKSEL_VIDEOPLL (0x03 << 1) 520 #define MGAREG_C2CTL_PIXCLKSEL_VDCLK (0x01 << 14) 521 522 #define MGAREG_C2CTL_PIXCLKSEL_CRISTAL (0x01 << 1) | (0x01 << 14) 523 #define MGAREG_C2CTL_PIXCLKSEL_SYSTEMPLL (0x02 << 1) | (0x01 << 14) 524 525 #define MGAREG_C2CTL_PIXCLKDIS_MASK (0x01 << 3) 526 #define MGAREG_C2CTL_PIXCLKDIS_DISABLE (0x01 << 3) 527 528 #define MGAREG_C2CTL_CRTCDACSEL_MASK (0x01 << 20) 529 #define MGAREG_C2CTL_CRTCDACSEL_CRTC1 0x00 530 #define MGAREG_C2CTL_CRTCDACSEL_CRTC2 (0x01 << 20) 531 532 #define MGAREG_C2HPARAM 0x3c14 533 #define MGAREG_C2HSYNC 0x3c18 534 #define MGAREG_C2VPARAM 0x3c1c 535 #define MGAREG_C2VSYNC 0x3c20 536 #define MGAREG_C2STARTADD0 0x3c28 537 538 #define MGAREG_C2OFFSET 0x3c40 539 #define MGAREG_C2DATACTL 0x3c4c 540 541 /* video register */ 542 543 #define MGAREG_BESA1C3ORG 0x3d60 544 #define MGAREG_BESA1CORG 0x3d10 545 #define MGAREG_BESA1ORG 0x3d00 546 #define MGAREG_BESCTL 0x3d20 547 #define MGAREG_BESGLOBCTL 0x3dc0 548 #define MGAREG_BESHCOORD 0x3d28 549 #define MGAREG_BESHISCAL 0x3d30 550 #define MGAREG_BESHSRCEND 0x3d3c 551 #define MGAREG_BESHSRCLST 0x3d50 552 #define MGAREG_BESHSRCST 0x3d38 553 #define MGAREG_BESLUMACTL 0x3d40 554 #define MGAREG_BESPITCH 0x3d24 555 #define MGAREG_BESV1SRCLST 0x3d54 556 #define MGAREG_BESV1WGHT 0x3d48 557 #define MGAREG_BESVCOORD 0x3d2c 558 #define MGAREG_BESVISCAL 0x3d34 559 560 /* texture engine registers */ 561 562 #define MGAREG_TMR0 0x2c00 563 #define MGAREG_TMR1 0x2c04 564 #define MGAREG_TMR2 0x2c08 565 #define MGAREG_TMR3 0x2c0c 566 #define MGAREG_TMR4 0x2c10 567 #define MGAREG_TMR5 0x2c14 568 #define MGAREG_TMR6 0x2c18 569 #define MGAREG_TMR7 0x2c1c 570 #define MGAREG_TMR8 0x2c20 571 #define MGAREG_TEXORG 0x2c24 572 #define MGAREG_TEXWIDTH 0x2c28 573 #define MGAREG_TEXHEIGHT 0x2c2c 574 #define MGAREG_TEXCTL 0x2c30 575 # define MGA_TW4 (0x00000000) 576 # define MGA_TW8 (0x00000001) 577 # define MGA_TW15 (0x00000002) 578 # define MGA_TW16 (0x00000003) 579 # define MGA_TW12 (0x00000004) 580 # define MGA_TW32 (0x00000006) 581 # define MGA_TW8A (0x00000007) 582 # define MGA_TW8AL (0x00000008) 583 # define MGA_TW422 (0x0000000A) 584 # define MGA_TW422UYVY (0x0000000B) 585 # define MGA_PITCHLIN (0x00000100) 586 # define MGA_NOPERSPECTIVE (0x00200000) 587 # define MGA_TAKEY (0x02000000) 588 # define MGA_TAMASK (0x04000000) 589 # define MGA_CLAMPUV (0x18000000) 590 # define MGA_TEXMODULATE (0x20000000) 591 #define MGAREG_TEXCTL2 0x2c3c 592 # define MGA_G400_TC2_MAGIC (0x00008000) 593 # define MGA_TC2_DECALBLEND (0x00000001) 594 # define MGA_TC2_IDECAL (0x00000002) 595 # define MGA_TC2_DECALDIS (0x00000004) 596 # define MGA_TC2_CKSTRANSDIS (0x00000010) 597 # define MGA_TC2_BORDEREN (0x00000020) 598 # define MGA_TC2_SPECEN (0x00000040) 599 # define MGA_TC2_DUALTEX (0x00000080) 600 # define MGA_TC2_TABLEFOG (0x00000100) 601 # define MGA_TC2_BUMPMAP (0x00000200) 602 # define MGA_TC2_SELECT_TMU1 (0x80000000) 603 #define MGAREG_TEXTRANS 0x2c34 604 #define MGAREG_TEXTRANSHIGH 0x2c38 605 #define MGAREG_TEXFILTER 0x2c58 606 # define MGA_MIN_NRST (0x00000000) 607 # define MGA_MIN_BILIN (0x00000002) 608 # define MGA_MIN_ANISO (0x0000000D) 609 # define MGA_MAG_NRST (0x00000000) 610 # define MGA_MAG_BILIN (0x00000020) 611 # define MGA_FILTERALPHA (0x00100000) 612 #define MGAREG_ALPHASTART 0x2c70 613 #define MGAREG_ALPHAXINC 0x2c74 614 #define MGAREG_ALPHAYINC 0x2c78 615 #define MGAREG_ALPHACTRL 0x2c7c 616 # define MGA_SRC_ZERO (0x00000000) 617 # define MGA_SRC_ONE (0x00000001) 618 # define MGA_SRC_DST_COLOR (0x00000002) 619 # define MGA_SRC_ONE_MINUS_DST_COLOR (0x00000003) 620 # define MGA_SRC_ALPHA (0x00000004) 621 # define MGA_SRC_ONE_MINUS_SRC_ALPHA (0x00000005) 622 # define MGA_SRC_DST_ALPHA (0x00000006) 623 # define MGA_SRC_ONE_MINUS_DST_ALPHA (0x00000007) 624 # define MGA_SRC_SRC_ALPHA_SATURATE (0x00000008) 625 # define MGA_SRC_BLEND_MASK (0x0000000f) 626 # define MGA_DST_ZERO (0x00000000) 627 # define MGA_DST_ONE (0x00000010) 628 # define MGA_DST_SRC_COLOR (0x00000020) 629 # define MGA_DST_ONE_MINUS_SRC_COLOR (0x00000030) 630 # define MGA_DST_SRC_ALPHA (0x00000040) 631 # define MGA_DST_ONE_MINUS_SRC_ALPHA (0x00000050) 632 # define MGA_DST_DST_ALPHA (0x00000060) 633 # define MGA_DST_ONE_MINUS_DST_ALPHA (0x00000070) 634 # define MGA_DST_BLEND_MASK (0x00000070) 635 # define MGA_ALPHACHANNEL (0x00000100) 636 # define MGA_VIDEOALPHA (0x00000200) 637 # define MGA_DIFFUSEDALPHA (0x01000000) 638 # define MGA_MODULATEDALPHA (0x02000000) 639 #define MGAREG_TDUALSTAGE0 (0x2CF8) 640 #define MGAREG_TDUALSTAGE1 (0x2CFC) 641 # define MGA_TDS_COLOR_ARG2_DIFFUSE (0x00000000) 642 # define MGA_TDS_COLOR_ARG2_SPECULAR (0x00000001) 643 # define MGA_TDS_COLOR_ARG2_FCOL (0x00000002) 644 # define MGA_TDS_COLOR_ARG2_PREVSTAGE (0x00000003) 645 # define MGA_TDS_COLOR_ALPHA_DIFFUSE (0x00000000) 646 # define MGA_TDS_COLOR_ALPHA_FCOL (0x00000004) 647 # define MGA_TDS_COLOR_ALPHA_CURRTEX (0x00000008) 648 # define MGA_TDS_COLOR_ALPHA_PREVTEX (0x0000000c) 649 # define MGA_TDS_COLOR_ALPHA_PREVSTAGE (0x00000010) 650 # define MGA_TDS_COLOR_ARG1_REPLICATEALPHA (0x00000020) 651 # define MGA_TDS_COLOR_ARG1_INV (0x00000040) 652 # define MGA_TDS_COLOR_ARG2_REPLICATEALPHA (0x00000080) 653 # define MGA_TDS_COLOR_ARG2_INV (0x00000100) 654 # define MGA_TDS_COLOR_ALPHA1INV (0x00000200) 655 # define MGA_TDS_COLOR_ALPHA2INV (0x00000400) 656 # define MGA_TDS_COLOR_ARG1MUL_ALPHA1 (0x00000800) 657 # define MGA_TDS_COLOR_ARG2MUL_ALPHA2 (0x00001000) 658 # define MGA_TDS_COLOR_ARG1ADD_MULOUT (0x00002000) 659 # define MGA_TDS_COLOR_ARG2ADD_MULOUT (0x00004000) 660 # define MGA_TDS_COLOR_MODBRIGHT_2X (0x00008000) 661 # define MGA_TDS_COLOR_MODBRIGHT_4X (0x00010000) 662 # define MGA_TDS_COLOR_ADD_SUB (0x00000000) 663 # define MGA_TDS_COLOR_ADD_ADD (0x00020000) 664 # define MGA_TDS_COLOR_ADD2X (0x00040000) 665 # define MGA_TDS_COLOR_ADDBIAS (0x00080000) 666 # define MGA_TDS_COLOR_BLEND (0x00100000) 667 # define MGA_TDS_COLOR_SEL_ARG1 (0x00000000) 668 # define MGA_TDS_COLOR_SEL_ARG2 (0x00200000) 669 # define MGA_TDS_COLOR_SEL_ADD (0x00400000) 670 # define MGA_TDS_COLOR_SEL_MUL (0x00600000) 671 # define MGA_TDS_ALPHA_ARG1_INV (0x00800000) 672 # define MGA_TDS_ALPHA_ARG2_DIFFUSE (0x00000000) 673 # define MGA_TDS_ALPHA_ARG2_FCOL (0x01000000) 674 # define MGA_TDS_ALPHA_ARG2_PREVTEX (0x02000000) 675 # define MGA_TDS_ALPHA_ARG2_PREVSTAGE (0x03000000) 676 # define MGA_TDS_ALPHA_ARG2_INV (0x04000000) 677 # define MGA_TDS_ALPHA_ADD (0x08000000) 678 # define MGA_TDS_ALPHA_ADDBIAS (0x10000000) 679 # define MGA_TDS_ALPHA_ADD2X (0x20000000) 680 # define MGA_TDS_ALPHA_SEL_ARG1 (0x00000000) 681 # define MGA_TDS_ALPHA_SEL_ARG2 (0x40000000) 682 # define MGA_TDS_ALPHA_SEL_ADD (0x80000000) 683 # define MGA_TDS_ALPHA_SEL_MUL (0xc0000000) 684 685 #define MGAREG_DWGSYNC 0x2c4c 686 687 #define MGAREG_AGP_PLL 0x1e4c 688 #define MGA_AGP2XPLL_ENABLE 0x1 689 #define MGA_AGP2XPLL_DISABLE 0x0 690 691 #endif 692