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Searched refs:MLXSW_ITEM32 (Results 1 – 7 of 7) sorted by relevance

/drivers/net/ethernet/mellanox/mlxsw/
Dcmd.h209 MLXSW_ITEM32(cmd_mbox, query_fw, fw_pages, 0x00, 16, 16);
214 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_major, 0x00, 0, 16);
219 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_subminor, 0x04, 16, 16);
224 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_minor, 0x04, 0, 16);
229 MLXSW_ITEM32(cmd_mbox, query_fw, core_clk, 0x08, 16, 16);
236 MLXSW_ITEM32(cmd_mbox, query_fw, cmd_interface_rev, 0x08, 0, 16);
241 MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1);
247 MLXSW_ITEM32(cmd_mbox, query_fw, api_version, 0x0C, 0, 16);
252 MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8);
257 MLXSW_ITEM32(cmd_mbox, query_fw, fw_minutes, 0x10, 16, 8);
[all …]
Dpci_hw.h74 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
86 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
91 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
143 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
144 MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
153 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
154 MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
155 MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
157 MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
158 MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
[all …]
Dreg.h47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
108 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
132 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
141 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
170 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
204 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
213 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
222 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
598 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
[all …]
Dcore_acl_flex_actions.c26 MLXSW_ITEM32(afa, set, type, 0xA0, 28, 4);
31 MLXSW_ITEM32(afa, set, next_action_set_ptr, 0xA4, 0, 24);
38 MLXSW_ITEM32(afa, set, goto_g, 0xA4, 29, 1);
50 MLXSW_ITEM32(afa, set, goto_binding_cmd, 0xA4, 24, 3);
56 MLXSW_ITEM32(afa, set, goto_next_binding, 0xA4, 0, 16);
61 MLXSW_ITEM32(afa, all, action_type, 0x00, 24, 6);
1102 MLXSW_ITEM32(afa, vlan, vlan_tag_cmd, 0x00, 29, 3);
1105 MLXSW_ITEM32(afa, vlan, vid_cmd, 0x04, 29, 3);
1108 MLXSW_ITEM32(afa, vlan, vid, 0x04, 0, 12);
1111 MLXSW_ITEM32(afa, vlan, ethertype_cmd, 0x08, 29, 3);
[all …]
Dcore.c283 MLXSW_ITEM32(emad, eth_hdr, ethertype, 0x0C, 16, 16);
289 MLXSW_ITEM32(emad, eth_hdr, mlx_proto, 0x0C, 8, 8);
295 MLXSW_ITEM32(emad, eth_hdr, ver, 0x0C, 4, 4);
301 MLXSW_ITEM32(emad, op_tlv, type, 0x00, 27, 5);
307 MLXSW_ITEM32(emad, op_tlv, len, 0x00, 16, 11);
315 MLXSW_ITEM32(emad, op_tlv, dr, 0x00, 15, 1);
332 MLXSW_ITEM32(emad, op_tlv, status, 0x00, 8, 7);
337 MLXSW_ITEM32(emad, op_tlv, register_id, 0x04, 16, 16);
342 MLXSW_ITEM32(emad, op_tlv, r, 0x04, 15, 1);
351 MLXSW_ITEM32(emad, op_tlv, method, 0x04, 8, 7);
[all …]
Dspectrum.c114 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
121 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
126 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
131 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
137 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
142 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
148 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
153 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
163 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
170 MLXSW_ITEM32(tx, hdr, fid, 0x08, 16, 16);
[all …]
Ditem.h352 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ macro