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Searched refs:MPLL_SS1 (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/radeon/
Drv740d.h110 #define MPLL_SS1 0x85c macro
Drv740_dpm.c313 pi->clk_regs.rv770.mpll_ss1 = RREG32(MPLL_SS1); in rv740_read_clock_registers()
Dnid.h687 #define MPLL_SS1 0x85c macro
Dsid.h630 #define MPLL_SS1 0x2bcc macro
Dcikd.h753 #define MPLL_SS1 0x2bcc macro
Devergreend.h225 #define MPLL_SS1 0x85c macro
Dni_dpm.c1195 ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in ni_read_clock_registers()
Dsi_dpm.c3565 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in si_read_clock_registers()
Dci_dpm.c1856 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in ci_read_clock_registers()
/drivers/gpu/drm/amd/amdgpu/
Dsid.h631 #define MPLL_SS1 0xAF3 macro
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Diceland_smumgr.c1140 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv); in iceland_calculate_mclk_params()
Dtonga_smumgr.c892 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv); in tonga_calculate_mclk_params()
Dci_smumgr.c1092 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv); in ci_calculate_mclk_params()
/drivers/gpu/drm/amd/pm/legacy-dpm/
Dsi_dpm.c4039 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in si_read_clock_registers()