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Searched refs:MTL_Q_RQOMR (Results 1 – 4 of 4) sorted by relevance

/drivers/net/ethernet/synopsys/
Ddwc-xlgmac-hw.c1196 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_disable_tx_flow_control()
1199 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_disable_tx_flow_control()
1228 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_enable_tx_flow_control()
1231 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_enable_tx_flow_control()
1333 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fep_enable()
1336 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fep_enable()
1346 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fup_enable()
1349 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fup_enable()
1464 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_threshold()
1467 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_threshold()
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Ddwc-xlgmac-reg.h394 #define MTL_Q_RQOMR 0x40 macro
/drivers/net/ethernet/amd/xgbe/
Dxgbe-dev.c227 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); in xgbe_config_rsf_mode()
248 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); in xgbe_config_rx_threshold()
545 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); in xgbe_disable_tx_flow_control()
582 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc); in xgbe_enable_tx_flow_control()
2637 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]); in xgbe_config_rx_fifo_size()
Dxgbe-common.h805 #define MTL_Q_RQOMR 0x40 macro