/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
D | dcn316_clk_mgr.c | 362 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn316_build_watermark_ranges() 365 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn316_build_watermark_ranges() 385 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in dcn316_build_watermark_ranges() 394 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; in dcn316_build_watermark_ranges()
|
D | dcn316_smu.h | 43 uint16_t MinMclk; member
|
/drivers/gpu/drm/amd/pm/powerplay/inc/ |
D | smu10_driver_if.h | 53 uint16_t MinMclk; member
|
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
D | vg_clk_mgr.c | 405 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in vg_build_watermark_ranges() 408 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in vg_build_watermark_ranges() 428 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in vg_build_watermark_ranges() 437 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; in vg_build_watermark_ranges()
|
D | dcn301_smu.h | 58 uint16_t MinMclk; member
|
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
D | dcn31_clk_mgr.c | 440 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn31_build_watermark_ranges() 443 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn31_build_watermark_ranges() 463 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in dcn31_build_watermark_ranges() 472 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; in dcn31_build_watermark_ranges()
|
D | dcn31_smu.h | 54 uint16_t MinMclk; member
|
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
D | dcn315_clk_mgr.c | 400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn315_build_watermark_ranges() 403 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn315_build_watermark_ranges() 423 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in dcn315_build_watermark_ranges() 432 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; in dcn315_build_watermark_ranges()
|
D | dcn315_smu.h | 44 uint16_t MinMclk; member
|
/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
D | smu13_driver_if_v13_0_5.h | 54 uint16_t MinMclk; member
|
D | smu13_driver_if_yellow_carp.h | 52 uint16_t MinMclk; member
|
D | smu12_driver_if.h | 53 uint16_t MinMclk; member
|
D | smu13_driver_if_v13_0_4.h | 53 uint16_t MinMclk; member
|
D | smu11_driver_if_vangogh.h | 52 uint16_t MinMclk; member
|
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
D | dcn314_clk_mgr.c | 455 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn314_build_watermark_ranges() 458 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn314_build_watermark_ranges() 478 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in dcn314_build_watermark_ranges() 487 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; in dcn314_build_watermark_ranges()
|
/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
D | smu_v13_0_5_ppt.c | 420 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in smu_v13_0_5_set_watermarks_table() 434 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in smu_v13_0_5_set_watermarks_table()
|
D | smu_v13_0_4_ppt.c | 676 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in smu_v13_0_4_set_watermarks_table() 690 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in smu_v13_0_4_set_watermarks_table()
|
D | yellow_carp_ppt.c | 511 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in yellow_carp_set_watermarks_table() 525 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in yellow_carp_set_watermarks_table()
|
/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
D | renoir_ppt.c | 1061 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in renoir_set_watermarks_table() 1077 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in renoir_set_watermarks_table()
|
/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
D | vangogh_ppt.c | 1642 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in vangogh_set_watermarks_table() 1656 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in vangogh_set_watermarks_table()
|