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1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2020-2022 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 #ifndef CPUCP_IF_H
9 #define CPUCP_IF_H
10 
11 #include <linux/types.h>
12 #include <linux/if_ether.h>
13 
14 #include "hl_boot_if.h"
15 
16 #define NUM_HBM_PSEUDO_CH				2
17 #define NUM_HBM_CH_PER_DEV				8
18 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_SHIFT		0
19 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK		0x00000001
20 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_SHIFT		1
21 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK		0x00000002
22 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_SHIFT		2
23 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK		0x00000004
24 #define CPUCP_PKT_HBM_ECC_INFO_DERR_SHIFT		3
25 #define CPUCP_PKT_HBM_ECC_INFO_DERR_MASK		0x00000008
26 #define CPUCP_PKT_HBM_ECC_INFO_SERR_SHIFT		4
27 #define CPUCP_PKT_HBM_ECC_INFO_SERR_MASK		0x00000010
28 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_SHIFT		5
29 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK		0x00000020
30 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_SHIFT		6
31 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK		0x000007C0
32 
33 #define PLL_MAP_MAX_BITS	128
34 #define PLL_MAP_LEN		(PLL_MAP_MAX_BITS / 8)
35 
36 /*
37  * info of the pkt queue pointers in the first async occurrence
38  */
39 struct cpucp_pkt_sync_err {
40 	__le32 pi;
41 	__le32 ci;
42 };
43 
44 struct hl_eq_hbm_ecc_data {
45 	/* SERR counter */
46 	__le32 sec_cnt;
47 	/* DERR counter */
48 	__le32 dec_cnt;
49 	/* Supplemental Information according to the mask bits */
50 	__le32 hbm_ecc_info;
51 	/* Address in hbm where the ecc happened */
52 	__le32 first_addr;
53 	/* SERR continuous address counter */
54 	__le32 sec_cont_cnt;
55 	__le32 pad;
56 };
57 
58 /*
59  * EVENT QUEUE
60  */
61 
62 struct hl_eq_header {
63 	__le32 reserved;
64 	__le32 ctl;
65 };
66 
67 struct hl_eq_ecc_data {
68 	__le64 ecc_address;
69 	__le64 ecc_syndrom;
70 	__u8 memory_wrapper_idx;
71 	__u8 is_critical;
72 	__u8 pad[6];
73 };
74 
75 enum hl_sm_sei_cause {
76 	SM_SEI_SO_OVERFLOW,
77 	SM_SEI_LBW_4B_UNALIGNED,
78 	SM_SEI_AXI_RESPONSE_ERR
79 };
80 
81 struct hl_eq_sm_sei_data {
82 	__le32 sei_log;
83 	/* enum hl_sm_sei_cause */
84 	__u8 sei_cause;
85 	__u8 pad[3];
86 };
87 
88 enum hl_fw_alive_severity {
89 	FW_ALIVE_SEVERITY_MINOR,
90 	FW_ALIVE_SEVERITY_CRITICAL
91 };
92 
93 struct hl_eq_fw_alive {
94 	__le64 uptime_seconds;
95 	__le32 process_id;
96 	__le32 thread_id;
97 	/* enum hl_fw_alive_severity */
98 	__u8 severity;
99 	__u8 pad[7];
100 };
101 
102 struct hl_eq_intr_cause {
103 	__le64 intr_cause_data;
104 };
105 
106 struct hl_eq_pcie_drain_ind_data {
107 	struct hl_eq_intr_cause intr_cause;
108 	__le64 drain_wr_addr_lbw;
109 	__le64 drain_rd_addr_lbw;
110 	__le64 drain_wr_addr_hbw;
111 	__le64 drain_rd_addr_hbw;
112 };
113 
114 struct hl_eq_razwi_lbw_info_regs {
115 	__le32 rr_aw_razwi_reg;
116 	__le32 rr_aw_razwi_id_reg;
117 	__le32 rr_ar_razwi_reg;
118 	__le32 rr_ar_razwi_id_reg;
119 };
120 
121 struct hl_eq_razwi_hbw_info_regs {
122 	__le32 rr_aw_razwi_hi_reg;
123 	__le32 rr_aw_razwi_lo_reg;
124 	__le32 rr_aw_razwi_id_reg;
125 	__le32 rr_ar_razwi_hi_reg;
126 	__le32 rr_ar_razwi_lo_reg;
127 	__le32 rr_ar_razwi_id_reg;
128 };
129 
130 /* razwi_happened masks */
131 #define RAZWI_HAPPENED_HBW	0x1
132 #define RAZWI_HAPPENED_LBW	0x2
133 #define RAZWI_HAPPENED_AW	0x4
134 #define RAZWI_HAPPENED_AR	0x8
135 
136 struct hl_eq_razwi_info {
137 	__le32 razwi_happened_mask;
138 	union {
139 		struct hl_eq_razwi_lbw_info_regs lbw;
140 		struct hl_eq_razwi_hbw_info_regs hbw;
141 	};
142 	__le32 pad;
143 };
144 
145 struct hl_eq_razwi_with_intr_cause {
146 	struct hl_eq_razwi_info razwi_info;
147 	struct hl_eq_intr_cause intr_cause;
148 };
149 
150 #define HBM_CA_ERR_CMD_LIFO_LEN		8
151 #define HBM_RD_ERR_DATA_LIFO_LEN	8
152 #define HBM_WR_PAR_CMD_LIFO_LEN		11
153 
154 enum hl_hbm_sei_cause {
155 	/* Command/address parity error event is split into 2 events due to
156 	 * size limitation: ODD suffix for odd HBM CK_t cycles and EVEN  suffix
157 	 * for even HBM CK_t cycles
158 	 */
159 	HBM_SEI_CMD_PARITY_EVEN,
160 	HBM_SEI_CMD_PARITY_ODD,
161 	/* Read errors can be reflected as a combination of SERR/DERR/parity
162 	 * errors. Therefore, we define one event for all read error types.
163 	 * LKD will perform further proccessing.
164 	 */
165 	HBM_SEI_READ_ERR,
166 	HBM_SEI_WRITE_DATA_PARITY_ERR,
167 	HBM_SEI_CATTRIP,
168 	HBM_SEI_MEM_BIST_FAIL,
169 	HBM_SEI_DFI,
170 	HBM_SEI_INV_TEMP_READ_OUT,
171 	HBM_SEI_BIST_FAIL,
172 };
173 
174 /* Masks for parsing hl_hbm_sei_headr fields */
175 #define HBM_ECC_SERR_CNTR_MASK		0xFF
176 #define HBM_ECC_DERR_CNTR_MASK		0xFF00
177 #define HBM_RD_PARITY_CNTR_MASK		0xFF0000
178 
179 /* HBM index and MC index are known by the event_id */
180 struct hl_hbm_sei_header {
181 	union {
182 		/* relevant only in case of HBM read error */
183 		struct {
184 			__u8 ecc_serr_cnt;
185 			__u8 ecc_derr_cnt;
186 			__u8 read_par_cnt;
187 			__u8 reserved;
188 		};
189 		/* All other cases */
190 		__le32 cnt;
191 	};
192 	__u8 sei_cause;		/* enum hl_hbm_sei_cause */
193 	__u8 mc_channel;		/* range: 0-3 */
194 	__u8 mc_pseudo_channel;	/* range: 0-7 */
195 	__u8 is_critical;
196 };
197 
198 #define HBM_RD_ADDR_SID_SHIFT		0
199 #define HBM_RD_ADDR_SID_MASK		0x1
200 #define HBM_RD_ADDR_BG_SHIFT		1
201 #define HBM_RD_ADDR_BG_MASK		0x6
202 #define HBM_RD_ADDR_BA_SHIFT		3
203 #define HBM_RD_ADDR_BA_MASK		0x18
204 #define HBM_RD_ADDR_COL_SHIFT		5
205 #define HBM_RD_ADDR_COL_MASK		0x7E0
206 #define HBM_RD_ADDR_ROW_SHIFT		11
207 #define HBM_RD_ADDR_ROW_MASK		0x3FFF800
208 
209 struct hbm_rd_addr {
210 	union {
211 		/* bit fields are only for FW use */
212 		struct {
213 			u32 dbg_rd_err_addr_sid:1;
214 			u32 dbg_rd_err_addr_bg:2;
215 			u32 dbg_rd_err_addr_ba:2;
216 			u32 dbg_rd_err_addr_col:6;
217 			u32 dbg_rd_err_addr_row:15;
218 			u32 reserved:6;
219 		};
220 		__le32 rd_addr_val;
221 	};
222 };
223 
224 #define HBM_RD_ERR_BEAT_SHIFT		2
225 /* dbg_rd_err_misc fields: */
226 /* Read parity is calculated per DW on every beat */
227 #define HBM_RD_ERR_PAR_ERR_BEAT0_SHIFT	0
228 #define HBM_RD_ERR_PAR_ERR_BEAT0_MASK	0x3
229 #define HBM_RD_ERR_PAR_DATA_BEAT0_SHIFT	8
230 #define HBM_RD_ERR_PAR_DATA_BEAT0_MASK	0x300
231 /* ECC is calculated per PC on every beat */
232 #define HBM_RD_ERR_SERR_BEAT0_SHIFT	16
233 #define HBM_RD_ERR_SERR_BEAT0_MASK	0x10000
234 #define HBM_RD_ERR_DERR_BEAT0_SHIFT	24
235 #define HBM_RD_ERR_DERR_BEAT0_MASK	0x100000
236 
237 struct hl_eq_hbm_sei_read_err_intr_info {
238 	/* DFI_RD_ERR_REP_ADDR */
239 	struct hbm_rd_addr dbg_rd_err_addr;
240 	/* DFI_RD_ERR_REP_ERR */
241 	union {
242 		struct {
243 			/* bit fields are only for FW use */
244 			u32 dbg_rd_err_par:8;
245 			u32 dbg_rd_err_par_data:8;
246 			u32 dbg_rd_err_serr:4;
247 			u32 dbg_rd_err_derr:4;
248 			u32 reserved:8;
249 		};
250 		__le32 dbg_rd_err_misc;
251 	};
252 	/* DFI_RD_ERR_REP_DM */
253 	__le32 dbg_rd_err_dm;
254 	/* DFI_RD_ERR_REP_SYNDROME */
255 	__le32 dbg_rd_err_syndrome;
256 	/* DFI_RD_ERR_REP_DATA */
257 	__le32 dbg_rd_err_data[HBM_RD_ERR_DATA_LIFO_LEN];
258 };
259 
260 struct hl_eq_hbm_sei_ca_par_intr_info {
261 	/* 14 LSBs */
262 	__le16 dbg_row[HBM_CA_ERR_CMD_LIFO_LEN];
263 	/* 18 LSBs */
264 	__le32 dbg_col[HBM_CA_ERR_CMD_LIFO_LEN];
265 };
266 
267 #define WR_PAR_LAST_CMD_COL_SHIFT	0
268 #define WR_PAR_LAST_CMD_COL_MASK	0x3F
269 #define WR_PAR_LAST_CMD_BG_SHIFT	6
270 #define WR_PAR_LAST_CMD_BG_MASK		0xC0
271 #define WR_PAR_LAST_CMD_BA_SHIFT	8
272 #define WR_PAR_LAST_CMD_BA_MASK		0x300
273 #define WR_PAR_LAST_CMD_SID_SHIFT	10
274 #define WR_PAR_LAST_CMD_SID_MASK	0x400
275 
276 /* Row address isn't latched */
277 struct hbm_sei_wr_cmd_address {
278 	/* DFI_DERR_LAST_CMD */
279 	union {
280 		struct {
281 			/* bit fields are only for FW use */
282 			u32 col:6;
283 			u32 bg:2;
284 			u32 ba:2;
285 			u32 sid:1;
286 			u32 reserved:21;
287 		};
288 		__le32 dbg_wr_cmd_addr;
289 	};
290 };
291 
292 struct hl_eq_hbm_sei_wr_par_intr_info {
293 	/* entry 0: WR command address from the 1st cycle prior to the error
294 	 * entry 1: WR command address from the 2nd cycle prior to the error
295 	 * and so on...
296 	 */
297 	struct hbm_sei_wr_cmd_address dbg_last_wr_cmds[HBM_WR_PAR_CMD_LIFO_LEN];
298 	/* derr[0:1] - 1st HBM cycle DERR output
299 	 * derr[2:3] - 2nd HBM cycle DERR output
300 	 */
301 	__u8 dbg_derr;
302 	/* extend to reach 8B */
303 	__u8 pad[3];
304 };
305 
306 /*
307  * this struct represents the following sei causes:
308  * command parity, ECC double error, ECC single error, dfi error, cattrip,
309  * temperature read-out, read parity error and write parity error.
310  * some only use the header while some have extra data.
311  */
312 struct hl_eq_hbm_sei_data {
313 	struct hl_hbm_sei_header hdr;
314 	union {
315 		struct hl_eq_hbm_sei_ca_par_intr_info ca_parity_even_info;
316 		struct hl_eq_hbm_sei_ca_par_intr_info ca_parity_odd_info;
317 		struct hl_eq_hbm_sei_read_err_intr_info read_err_info;
318 		struct hl_eq_hbm_sei_wr_par_intr_info wr_parity_info;
319 	};
320 };
321 
322 /* Engine/farm arc interrupt type */
323 enum hl_engine_arc_interrupt_type {
324 	/* Qman/farm ARC DCCM QUEUE FULL interrupt type */
325 	ENGINE_ARC_DCCM_QUEUE_FULL_IRQ = 1
326 };
327 
328 /* Data structure specifies details of payload of DCCM QUEUE FULL interrupt */
329 struct hl_engine_arc_dccm_queue_full_irq {
330 	/* Queue index value which caused DCCM QUEUE FULL */
331 	__le32 queue_index;
332 	__le32 pad;
333 };
334 
335 /* Data structure specifies details of QM/FARM ARC interrupt */
336 struct hl_eq_engine_arc_intr_data {
337 	/* ARC engine id e.g.  DCORE0_TPC0_QM_ARC, DCORE0_TCP1_QM_ARC */
338 	__le32 engine_id;
339 	__le32 intr_type; /* enum hl_engine_arc_interrupt_type */
340 	/* More info related to the interrupt e.g. queue index
341 	 * incase of DCCM_QUEUE_FULL interrupt.
342 	 */
343 	__le64 payload;
344 	__le64 pad[5];
345 };
346 
347 #define ADDR_DEC_ADDRESS_COUNT_MAX 4
348 
349 /* Data structure specifies details of ADDR_DEC interrupt */
350 struct hl_eq_addr_dec_intr_data {
351 	struct hl_eq_intr_cause intr_cause;
352 	__le64 addr[ADDR_DEC_ADDRESS_COUNT_MAX];
353 	__u8 addr_cnt;
354 	__u8 pad[7];
355 };
356 
357 struct hl_eq_entry {
358 	struct hl_eq_header hdr;
359 	union {
360 		__le64 data_placeholder;
361 		struct hl_eq_ecc_data ecc_data;
362 		struct hl_eq_hbm_ecc_data hbm_ecc_data;	/* Obsolete */
363 		struct hl_eq_sm_sei_data sm_sei_data;
364 		struct cpucp_pkt_sync_err pkt_sync_err;
365 		struct hl_eq_fw_alive fw_alive;
366 		struct hl_eq_intr_cause intr_cause;
367 		struct hl_eq_pcie_drain_ind_data pcie_drain_ind_data;
368 		struct hl_eq_razwi_info razwi_info;
369 		struct hl_eq_razwi_with_intr_cause razwi_with_intr_cause;
370 		struct hl_eq_hbm_sei_data sei_data;	/* Gaudi2 HBM */
371 		struct hl_eq_engine_arc_intr_data arc_data;
372 		struct hl_eq_addr_dec_intr_data addr_dec;
373 		__le64 data[7];
374 	};
375 };
376 
377 #define HL_EQ_ENTRY_SIZE		sizeof(struct hl_eq_entry)
378 
379 #define EQ_CTL_READY_SHIFT		31
380 #define EQ_CTL_READY_MASK		0x80000000
381 
382 #define EQ_CTL_EVENT_TYPE_SHIFT		16
383 #define EQ_CTL_EVENT_TYPE_MASK		0x0FFF0000
384 
385 #define EQ_CTL_INDEX_SHIFT		0
386 #define EQ_CTL_INDEX_MASK		0x0000FFFF
387 
388 enum pq_init_status {
389 	PQ_INIT_STATUS_NA = 0,
390 	PQ_INIT_STATUS_READY_FOR_CP,
391 	PQ_INIT_STATUS_READY_FOR_HOST,
392 	PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI,
393 	PQ_INIT_STATUS_LEN_NOT_POWER_OF_TWO_ERR,
394 	PQ_INIT_STATUS_ILLEGAL_Q_ADDR_ERR
395 };
396 
397 /*
398  * CpuCP Primary Queue Packets
399  *
400  * During normal operation, the host's kernel driver needs to send various
401  * messages to CpuCP, usually either to SET some value into a H/W periphery or
402  * to GET the current value of some H/W periphery. For example, SET the
403  * frequency of MME/TPC and GET the value of the thermal sensor.
404  *
405  * These messages can be initiated either by the User application or by the
406  * host's driver itself, e.g. power management code. In either case, the
407  * communication from the host's driver to CpuCP will *always* be in
408  * synchronous mode, meaning that the host will send a single message and poll
409  * until the message was acknowledged and the results are ready (if results are
410  * needed).
411  *
412  * This means that only a single message can be sent at a time and the host's
413  * driver must wait for its result before sending the next message. Having said
414  * that, because these are control messages which are sent in a relatively low
415  * frequency, this limitation seems acceptable. It's important to note that
416  * in case of multiple devices, messages to different devices *can* be sent
417  * at the same time.
418  *
419  * The message, inputs/outputs (if relevant) and fence object will be located
420  * on the device DDR at an address that will be determined by the host's driver.
421  * During device initialization phase, the host will pass to CpuCP that address.
422  * Most of the message types will contain inputs/outputs inside the message
423  * itself. The common part of each message will contain the opcode of the
424  * message (its type) and a field representing a fence object.
425  *
426  * When the host's driver wishes to send a message to CPU CP, it will write the
427  * message contents to the device DDR, clear the fence object and then write to
428  * the PSOC_ARC1_AUX_SW_INTR, to issue interrupt 121 to ARC Management CPU.
429  *
430  * Upon receiving the interrupt (#121), CpuCP will read the message from the
431  * DDR. In case the message is a SET operation, CpuCP will first perform the
432  * operation and then write to the fence object on the device DDR. In case the
433  * message is a GET operation, CpuCP will first fill the results section on the
434  * device DDR and then write to the fence object. If an error occurred, CpuCP
435  * will fill the rc field with the right error code.
436  *
437  * In the meantime, the host's driver will poll on the fence object. Once the
438  * host sees that the fence object is signaled, it will read the results from
439  * the device DDR (if relevant) and resume the code execution in the host's
440  * driver.
441  *
442  * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8
443  * so the value being put by the host's driver matches the value read by CpuCP
444  *
445  * Non-QMAN packets should be limited to values 1 through (2^8 - 1)
446  *
447  * Detailed description:
448  *
449  * CPUCP_PACKET_DISABLE_PCI_ACCESS -
450  *       After receiving this packet the embedded CPU must NOT issue PCI
451  *       transactions (read/write) towards the Host CPU. This also include
452  *       sending MSI-X interrupts.
453  *       This packet is usually sent before the device is moved to D3Hot state.
454  *
455  * CPUCP_PACKET_ENABLE_PCI_ACCESS -
456  *       After receiving this packet the embedded CPU is allowed to issue PCI
457  *       transactions towards the Host CPU, including sending MSI-X interrupts.
458  *       This packet is usually send after the device is moved to D0 state.
459  *
460  * CPUCP_PACKET_TEMPERATURE_GET -
461  *       Fetch the current temperature / Max / Max Hyst / Critical /
462  *       Critical Hyst of a specified thermal sensor. The packet's
463  *       arguments specify the desired sensor and the field to get.
464  *
465  * CPUCP_PACKET_VOLTAGE_GET -
466  *       Fetch the voltage / Max / Min of a specified sensor. The packet's
467  *       arguments specify the sensor and type.
468  *
469  * CPUCP_PACKET_CURRENT_GET -
470  *       Fetch the current / Max / Min of a specified sensor. The packet's
471  *       arguments specify the sensor and type.
472  *
473  * CPUCP_PACKET_FAN_SPEED_GET -
474  *       Fetch the speed / Max / Min of a specified fan. The packet's
475  *       arguments specify the sensor and type.
476  *
477  * CPUCP_PACKET_PWM_GET -
478  *       Fetch the pwm value / mode of a specified pwm. The packet's
479  *       arguments specify the sensor and type.
480  *
481  * CPUCP_PACKET_PWM_SET -
482  *       Set the pwm value / mode of a specified pwm. The packet's
483  *       arguments specify the sensor, type and value.
484  *
485  * CPUCP_PACKET_FREQUENCY_SET -
486  *       Set the frequency of a specified PLL. The packet's arguments specify
487  *       the PLL and the desired frequency. The actual frequency in the device
488  *       might differ from the requested frequency.
489  *
490  * CPUCP_PACKET_FREQUENCY_GET -
491  *       Fetch the frequency of a specified PLL. The packet's arguments specify
492  *       the PLL.
493  *
494  * CPUCP_PACKET_LED_SET -
495  *       Set the state of a specified led. The packet's arguments
496  *       specify the led and the desired state.
497  *
498  * CPUCP_PACKET_I2C_WR -
499  *       Write 32-bit value to I2C device. The packet's arguments specify the
500  *       I2C bus, address and value.
501  *
502  * CPUCP_PACKET_I2C_RD -
503  *       Read 32-bit value from I2C device. The packet's arguments specify the
504  *       I2C bus and address.
505  *
506  * CPUCP_PACKET_INFO_GET -
507  *       Fetch information from the device as specified in the packet's
508  *       structure. The host's driver passes the max size it allows the CpuCP to
509  *       write to the structure, to prevent data corruption in case of
510  *       mismatched driver/FW versions.
511  *
512  * CPUCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed
513  *
514  * CPUCP_PACKET_UNMASK_RAZWI_IRQ -
515  *       Unmask the given IRQ. The IRQ number is specified in the value field.
516  *       The packet is sent after receiving an interrupt and printing its
517  *       relevant information.
518  *
519  * CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY -
520  *       Unmask the given IRQs. The IRQs numbers are specified in an array right
521  *       after the cpucp_packet structure, where its first element is the array
522  *       length. The packet is sent after a soft reset was done in order to
523  *       handle any interrupts that were sent during the reset process.
524  *
525  * CPUCP_PACKET_TEST -
526  *       Test packet for CpuCP connectivity. The CPU will put the fence value
527  *       in the result field.
528  *
529  * CPUCP_PACKET_FREQUENCY_CURR_GET -
530  *       Fetch the current frequency of a specified PLL. The packet's arguments
531  *       specify the PLL.
532  *
533  * CPUCP_PACKET_MAX_POWER_GET -
534  *       Fetch the maximal power of the device.
535  *
536  * CPUCP_PACKET_MAX_POWER_SET -
537  *       Set the maximal power of the device. The packet's arguments specify
538  *       the power.
539  *
540  * CPUCP_PACKET_EEPROM_DATA_GET -
541  *       Get EEPROM data from the CpuCP kernel. The buffer is specified in the
542  *       addr field. The CPU will put the returned data size in the result
543  *       field. In addition, the host's driver passes the max size it allows the
544  *       CpuCP to write to the structure, to prevent data corruption in case of
545  *       mismatched driver/FW versions.
546  *
547  * CPUCP_PACKET_NIC_INFO_GET -
548  *       Fetch information from the device regarding the NIC. the host's driver
549  *       passes the max size it allows the CpuCP to write to the structure, to
550  *       prevent data corruption in case of mismatched driver/FW versions.
551  *
552  * CPUCP_PACKET_TEMPERATURE_SET -
553  *       Set the value of the offset property of a specified thermal sensor.
554  *       The packet's arguments specify the desired sensor and the field to
555  *       set.
556  *
557  * CPUCP_PACKET_VOLTAGE_SET -
558  *       Trigger the reset_history property of a specified voltage sensor.
559  *       The packet's arguments specify the desired sensor and the field to
560  *       set.
561  *
562  * CPUCP_PACKET_CURRENT_SET -
563  *       Trigger the reset_history property of a specified current sensor.
564  *       The packet's arguments specify the desired sensor and the field to
565  *       set.
566  *
567  * CPUCP_PACKET_PCIE_THROUGHPUT_GET -
568  *       Get throughput of PCIe.
569  *       The packet's arguments specify the transaction direction (TX/RX).
570  *       The window measurement is 10[msec], and the return value is in KB/sec.
571  *
572  * CPUCP_PACKET_PCIE_REPLAY_CNT_GET
573  *       Replay count measures number of "replay" events, which is basicly
574  *       number of retries done by PCIe.
575  *
576  * CPUCP_PACKET_TOTAL_ENERGY_GET -
577  *       Total Energy is measurement of energy from the time FW Linux
578  *       is loaded. It is calculated by multiplying the average power
579  *       by time (passed from armcp start). The units are in MilliJouls.
580  *
581  * CPUCP_PACKET_PLL_INFO_GET -
582  *       Fetch frequencies of PLL from the required PLL IP.
583  *       The packet's arguments specify the device PLL type
584  *       Pll type is the PLL from device pll_index enum.
585  *       The result is composed of 4 outputs, each is 16-bit
586  *       frequency in MHz.
587  *
588  * CPUCP_PACKET_POWER_GET -
589  *       Fetch the present power consumption of the device (Current * Voltage).
590  *
591  * CPUCP_PACKET_NIC_PFC_SET -
592  *       Enable/Disable the NIC PFC feature. The packet's arguments specify the
593  *       NIC port, relevant lanes to configure and one bit indication for
594  *       enable/disable.
595  *
596  * CPUCP_PACKET_NIC_FAULT_GET -
597  *       Fetch the current indication for local/remote faults from the NIC MAC.
598  *       The result is 32-bit value of the relevant register.
599  *
600  * CPUCP_PACKET_NIC_LPBK_SET -
601  *       Enable/Disable the MAC loopback feature. The packet's arguments specify
602  *       the NIC port, relevant lanes to configure and one bit indication for
603  *       enable/disable.
604  *
605  * CPUCP_PACKET_NIC_MAC_INIT -
606  *       Configure the NIC MAC channels. The packet's arguments specify the
607  *       NIC port and the speed.
608  *
609  * CPUCP_PACKET_MSI_INFO_SET -
610  *       set the index number for each supported msi type going from
611  *       host to device
612  *
613  * CPUCP_PACKET_NIC_XPCS91_REGS_GET -
614  *       Fetch the un/correctable counters values from the NIC MAC.
615  *
616  * CPUCP_PACKET_NIC_STAT_REGS_GET -
617  *       Fetch various NIC MAC counters from the NIC STAT.
618  *
619  * CPUCP_PACKET_NIC_STAT_REGS_CLR -
620  *       Clear the various NIC MAC counters in the NIC STAT.
621  *
622  * CPUCP_PACKET_NIC_STAT_REGS_ALL_GET -
623  *       Fetch all NIC MAC counters from the NIC STAT.
624  *
625  * CPUCP_PACKET_IS_IDLE_CHECK -
626  *       Check if the device is IDLE in regard to the DMA/compute engines
627  *       and QMANs. The f/w will return a bitmask where each bit represents
628  *       a different engine or QMAN according to enum cpucp_idle_mask.
629  *       The bit will be 1 if the engine is NOT idle.
630  *
631  * CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET -
632  *       Fetch all HBM replaced-rows and prending to be replaced rows data.
633  *
634  * CPUCP_PACKET_HBM_PENDING_ROWS_STATUS -
635  *       Fetch status of HBM rows pending replacement and need a reboot to
636  *       be replaced.
637  *
638  * CPUCP_PACKET_POWER_SET -
639  *       Resets power history of device to 0
640  *
641  * CPUCP_PACKET_ENGINE_CORE_ASID_SET -
642  *       Packet to perform engine core ASID configuration
643  *
644  * CPUCP_PACKET_SEC_ATTEST_GET -
645  *       Get the attestaion data that is collected during various stages of the
646  *       boot sequence. the attestation data is also hashed with some unique
647  *       number (nonce) provided by the host to prevent replay attacks.
648  *       public key and certificate also provided as part of the FW response.
649  *
650  * CPUCP_PACKET_MONITOR_DUMP_GET -
651  *       Get monitors registers dump from the CpuCP kernel.
652  *       The CPU will put the registers dump in the a buffer allocated by the driver
653  *       which address is passed via the CpuCp packet. In addition, the host's driver
654  *       passes the max size it allows the CpuCP to write to the structure, to prevent
655  *       data corruption in case of mismatched driver/FW versions.
656  *       Obsolete.
657  *
658  * CPUCP_PACKET_GENERIC_PASSTHROUGH -
659  *      Generic opcode for all firmware info that is only passed to host
660  *      through the LKD, without getting parsed there.
661  *
662  * CPUCP_PACKET_ACTIVE_STATUS_SET -
663  *       LKD sends FW indication whether device is free or in use, this indication is reported
664  *       also to the BMC.
665  *
666  * CPUCP_PACKET_REGISTER_INTERRUPTS -
667  *       Packet to register interrupts indicating LKD is ready to receive events from FW.
668  *
669  * CPUCP_PACKET_SOFT_RESET -
670  *	 Packet to perform soft-reset.
671  */
672 
673 enum cpucp_packet_id {
674 	CPUCP_PACKET_DISABLE_PCI_ACCESS = 1,	/* internal */
675 	CPUCP_PACKET_ENABLE_PCI_ACCESS,		/* internal */
676 	CPUCP_PACKET_TEMPERATURE_GET,		/* sysfs */
677 	CPUCP_PACKET_VOLTAGE_GET,		/* sysfs */
678 	CPUCP_PACKET_CURRENT_GET,		/* sysfs */
679 	CPUCP_PACKET_FAN_SPEED_GET,		/* sysfs */
680 	CPUCP_PACKET_PWM_GET,			/* sysfs */
681 	CPUCP_PACKET_PWM_SET,			/* sysfs */
682 	CPUCP_PACKET_FREQUENCY_SET,		/* sysfs */
683 	CPUCP_PACKET_FREQUENCY_GET,		/* sysfs */
684 	CPUCP_PACKET_LED_SET,			/* debugfs */
685 	CPUCP_PACKET_I2C_WR,			/* debugfs */
686 	CPUCP_PACKET_I2C_RD,			/* debugfs */
687 	CPUCP_PACKET_INFO_GET,			/* IOCTL */
688 	CPUCP_PACKET_FLASH_PROGRAM_REMOVED,
689 	CPUCP_PACKET_UNMASK_RAZWI_IRQ,		/* internal */
690 	CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY,	/* internal */
691 	CPUCP_PACKET_TEST,			/* internal */
692 	CPUCP_PACKET_FREQUENCY_CURR_GET,	/* sysfs */
693 	CPUCP_PACKET_MAX_POWER_GET,		/* sysfs */
694 	CPUCP_PACKET_MAX_POWER_SET,		/* sysfs */
695 	CPUCP_PACKET_EEPROM_DATA_GET,		/* sysfs */
696 	CPUCP_PACKET_NIC_INFO_GET,		/* internal */
697 	CPUCP_PACKET_TEMPERATURE_SET,		/* sysfs */
698 	CPUCP_PACKET_VOLTAGE_SET,		/* sysfs */
699 	CPUCP_PACKET_CURRENT_SET,		/* sysfs */
700 	CPUCP_PACKET_PCIE_THROUGHPUT_GET,	/* internal */
701 	CPUCP_PACKET_PCIE_REPLAY_CNT_GET,	/* internal */
702 	CPUCP_PACKET_TOTAL_ENERGY_GET,		/* internal */
703 	CPUCP_PACKET_PLL_INFO_GET,		/* internal */
704 	CPUCP_PACKET_NIC_STATUS,		/* internal */
705 	CPUCP_PACKET_POWER_GET,			/* internal */
706 	CPUCP_PACKET_NIC_PFC_SET,		/* internal */
707 	CPUCP_PACKET_NIC_FAULT_GET,		/* internal */
708 	CPUCP_PACKET_NIC_LPBK_SET,		/* internal */
709 	CPUCP_PACKET_NIC_MAC_CFG,		/* internal */
710 	CPUCP_PACKET_MSI_INFO_SET,		/* internal */
711 	CPUCP_PACKET_NIC_XPCS91_REGS_GET,	/* internal */
712 	CPUCP_PACKET_NIC_STAT_REGS_GET,		/* internal */
713 	CPUCP_PACKET_NIC_STAT_REGS_CLR,		/* internal */
714 	CPUCP_PACKET_NIC_STAT_REGS_ALL_GET,	/* internal */
715 	CPUCP_PACKET_IS_IDLE_CHECK,		/* internal */
716 	CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET,/* internal */
717 	CPUCP_PACKET_HBM_PENDING_ROWS_STATUS,	/* internal */
718 	CPUCP_PACKET_POWER_SET,			/* internal */
719 	CPUCP_PACKET_RESERVED,			/* not used */
720 	CPUCP_PACKET_ENGINE_CORE_ASID_SET,	/* internal */
721 	CPUCP_PACKET_RESERVED2,			/* not used */
722 	CPUCP_PACKET_SEC_ATTEST_GET,		/* internal */
723 	CPUCP_PACKET_RESERVED3,			/* not used */
724 	CPUCP_PACKET_RESERVED4,			/* not used */
725 	CPUCP_PACKET_MONITOR_DUMP_GET,		/* debugfs */
726 	CPUCP_PACKET_RESERVED5,			/* not used */
727 	CPUCP_PACKET_RESERVED6,			/* not used */
728 	CPUCP_PACKET_RESERVED7,			/* not used */
729 	CPUCP_PACKET_GENERIC_PASSTHROUGH,	/* IOCTL */
730 	CPUCP_PACKET_RESERVED8,			/* not used */
731 	CPUCP_PACKET_ACTIVE_STATUS_SET,		/* internal */
732 	CPUCP_PACKET_RESERVED9,			/* not used */
733 	CPUCP_PACKET_RESERVED10,		/* not used */
734 	CPUCP_PACKET_RESERVED11,		/* not used */
735 	CPUCP_PACKET_RESERVED12,		/* internal */
736 	CPUCP_PACKET_REGISTER_INTERRUPTS,	/* internal */
737 	CPUCP_PACKET_SOFT_RESET,		/* internal */
738 	CPUCP_PACKET_ID_MAX			/* must be last */
739 };
740 
741 #define CPUCP_PACKET_FENCE_VAL	0xFE8CE7A5
742 
743 #define CPUCP_PKT_CTL_RC_SHIFT		12
744 #define CPUCP_PKT_CTL_RC_MASK		0x0000F000
745 
746 #define CPUCP_PKT_CTL_OPCODE_SHIFT	16
747 #define CPUCP_PKT_CTL_OPCODE_MASK	0x1FFF0000
748 
749 #define CPUCP_PKT_RES_PLL_OUT0_SHIFT	0
750 #define CPUCP_PKT_RES_PLL_OUT0_MASK	0x000000000000FFFFull
751 #define CPUCP_PKT_RES_PLL_OUT1_SHIFT	16
752 #define CPUCP_PKT_RES_PLL_OUT1_MASK	0x00000000FFFF0000ull
753 #define CPUCP_PKT_RES_PLL_OUT2_SHIFT	32
754 #define CPUCP_PKT_RES_PLL_OUT2_MASK	0x0000FFFF00000000ull
755 #define CPUCP_PKT_RES_PLL_OUT3_SHIFT	48
756 #define CPUCP_PKT_RES_PLL_OUT3_MASK	0xFFFF000000000000ull
757 
758 #define CPUCP_PKT_RES_EEPROM_OUT0_SHIFT	0
759 #define CPUCP_PKT_RES_EEPROM_OUT0_MASK	0x000000000000FFFFull
760 #define CPUCP_PKT_RES_EEPROM_OUT1_SHIFT	16
761 #define CPUCP_PKT_RES_EEPROM_OUT1_MASK	0x0000000000FF0000ull
762 
763 #define CPUCP_PKT_VAL_PFC_IN1_SHIFT	0
764 #define CPUCP_PKT_VAL_PFC_IN1_MASK	0x0000000000000001ull
765 #define CPUCP_PKT_VAL_PFC_IN2_SHIFT	1
766 #define CPUCP_PKT_VAL_PFC_IN2_MASK	0x000000000000001Eull
767 
768 #define CPUCP_PKT_VAL_LPBK_IN1_SHIFT	0
769 #define CPUCP_PKT_VAL_LPBK_IN1_MASK	0x0000000000000001ull
770 #define CPUCP_PKT_VAL_LPBK_IN2_SHIFT	1
771 #define CPUCP_PKT_VAL_LPBK_IN2_MASK	0x000000000000001Eull
772 
773 #define CPUCP_PKT_VAL_MAC_CNT_IN1_SHIFT	0
774 #define CPUCP_PKT_VAL_MAC_CNT_IN1_MASK	0x0000000000000001ull
775 #define CPUCP_PKT_VAL_MAC_CNT_IN2_SHIFT	1
776 #define CPUCP_PKT_VAL_MAC_CNT_IN2_MASK	0x00000000FFFFFFFEull
777 
778 /* heartbeat status bits */
779 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_SHIFT		0
780 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_MASK		0x00000001
781 
782 struct cpucp_packet {
783 	union {
784 		__le64 value;	/* For SET packets */
785 		__le64 result;	/* For GET packets */
786 		__le64 addr;	/* For PQ */
787 	};
788 
789 	__le32 ctl;
790 
791 	__le32 fence;		/* Signal to host that message is completed */
792 
793 	union {
794 		struct {/* For temperature/current/voltage/fan/pwm get/set */
795 			__le16 sensor_index;
796 			__le16 type;
797 		};
798 
799 		struct {	/* For I2C read/write */
800 			__u8 i2c_bus;
801 			__u8 i2c_addr;
802 			__u8 i2c_reg;
803 			/*
804 			 * In legacy implemetations, i2c_len was not present,
805 			 * was unused and just added as pad.
806 			 * So if i2c_len is 0, it is treated as legacy
807 			 * and r/w 1 Byte, else if i2c_len is specified,
808 			 * its treated as new multibyte r/w support.
809 			 */
810 			__u8 i2c_len;
811 		};
812 
813 		struct {/* For PLL info fetch */
814 			__le16 pll_type;
815 			/* TODO pll_reg is kept temporary before removal */
816 			__le16 pll_reg;
817 		};
818 
819 		/* For any general request */
820 		__le32 index;
821 
822 		/* For frequency get/set */
823 		__le32 pll_index;
824 
825 		/* For led set */
826 		__le32 led_index;
827 
828 		/* For get CpuCP info/EEPROM data/NIC info */
829 		__le32 data_max_size;
830 
831 		/*
832 		 * For any general status bitmask. Shall be used whenever the
833 		 * result cannot be used to hold general purpose data.
834 		 */
835 		__le32 status_mask;
836 
837 		/* random, used once number, for security packets */
838 		__le32 nonce;
839 	};
840 
841 	union {
842 		/* For NIC requests */
843 		__le32 port_index;
844 
845 		/* For Generic packet sub index */
846 		__le32 pkt_subidx;
847 	};
848 };
849 
850 struct cpucp_unmask_irq_arr_packet {
851 	struct cpucp_packet cpucp_pkt;
852 	__le32 length;
853 	__le32 irqs[];
854 };
855 
856 struct cpucp_nic_status_packet {
857 	struct cpucp_packet cpucp_pkt;
858 	__le32 length;
859 	__le32 data[];
860 };
861 
862 struct cpucp_array_data_packet {
863 	struct cpucp_packet cpucp_pkt;
864 	__le32 length;
865 	__le32 data[];
866 };
867 
868 enum cpucp_led_index {
869 	CPUCP_LED0_INDEX = 0,
870 	CPUCP_LED1_INDEX,
871 	CPUCP_LED2_INDEX,
872 	CPUCP_LED_MAX_INDEX = CPUCP_LED2_INDEX
873 };
874 
875 /*
876  * enum cpucp_packet_rc - Error return code
877  * @cpucp_packet_success	-> in case of success.
878  * @cpucp_packet_invalid	-> this is to support first generation platforms.
879  * @cpucp_packet_fault		-> in case of processing error like failing to
880  *                                 get device binding or semaphore etc.
881  * @cpucp_packet_invalid_pkt	-> when cpucp packet is un-supported.
882  * @cpucp_packet_invalid_params	-> when checking parameter like length of buffer
883  *				   or attribute value etc.
884  * @cpucp_packet_rc_max		-> It indicates size of enum so should be at last.
885  */
886 enum cpucp_packet_rc {
887 	cpucp_packet_success,
888 	cpucp_packet_invalid,
889 	cpucp_packet_fault,
890 	cpucp_packet_invalid_pkt,
891 	cpucp_packet_invalid_params,
892 	cpucp_packet_rc_max
893 };
894 
895 /*
896  * cpucp_temp_type should adhere to hwmon_temp_attributes
897  * defined in Linux kernel hwmon.h file
898  */
899 enum cpucp_temp_type {
900 	cpucp_temp_input,
901 	cpucp_temp_min = 4,
902 	cpucp_temp_min_hyst,
903 	cpucp_temp_max = 6,
904 	cpucp_temp_max_hyst,
905 	cpucp_temp_crit,
906 	cpucp_temp_crit_hyst,
907 	cpucp_temp_offset = 19,
908 	cpucp_temp_lowest = 21,
909 	cpucp_temp_highest = 22,
910 	cpucp_temp_reset_history = 23,
911 	cpucp_temp_warn = 24,
912 	cpucp_temp_max_crit = 25,
913 	cpucp_temp_max_warn = 26,
914 };
915 
916 enum cpucp_in_attributes {
917 	cpucp_in_input,
918 	cpucp_in_min,
919 	cpucp_in_max,
920 	cpucp_in_lowest = 6,
921 	cpucp_in_highest = 7,
922 	cpucp_in_reset_history,
923 	cpucp_in_intr_alarm_a,
924 	cpucp_in_intr_alarm_b,
925 };
926 
927 enum cpucp_curr_attributes {
928 	cpucp_curr_input,
929 	cpucp_curr_min,
930 	cpucp_curr_max,
931 	cpucp_curr_lowest = 6,
932 	cpucp_curr_highest = 7,
933 	cpucp_curr_reset_history
934 };
935 
936 enum cpucp_fan_attributes {
937 	cpucp_fan_input,
938 	cpucp_fan_min = 2,
939 	cpucp_fan_max
940 };
941 
942 enum cpucp_pwm_attributes {
943 	cpucp_pwm_input,
944 	cpucp_pwm_enable
945 };
946 
947 enum cpucp_pcie_throughput_attributes {
948 	cpucp_pcie_throughput_tx,
949 	cpucp_pcie_throughput_rx
950 };
951 
952 /* TODO temporary kept before removal */
953 enum cpucp_pll_reg_attributes {
954 	cpucp_pll_nr_reg,
955 	cpucp_pll_nf_reg,
956 	cpucp_pll_od_reg,
957 	cpucp_pll_div_factor_reg,
958 	cpucp_pll_div_sel_reg
959 };
960 
961 /* TODO temporary kept before removal */
962 enum cpucp_pll_type_attributes {
963 	cpucp_pll_cpu,
964 	cpucp_pll_pci,
965 };
966 
967 /*
968  * cpucp_power_type aligns with hwmon_power_attributes
969  * defined in Linux kernel hwmon.h file
970  */
971 enum cpucp_power_type {
972 	CPUCP_POWER_INPUT = 8,
973 	CPUCP_POWER_INPUT_HIGHEST = 9,
974 	CPUCP_POWER_RESET_INPUT_HISTORY = 11
975 };
976 
977 /*
978  * MSI type enumeration table for all ASICs and future SW versions.
979  * For future ASIC-LKD compatibility, we can only add new enumerations.
980  * at the end of the table (before CPUCP_NUM_OF_MSI_TYPES).
981  * Changing the order of entries or removing entries is not allowed.
982  */
983 enum cpucp_msi_type {
984 	CPUCP_EVENT_QUEUE_MSI_TYPE,
985 	CPUCP_NIC_PORT1_MSI_TYPE,
986 	CPUCP_NIC_PORT3_MSI_TYPE,
987 	CPUCP_NIC_PORT5_MSI_TYPE,
988 	CPUCP_NIC_PORT7_MSI_TYPE,
989 	CPUCP_NIC_PORT9_MSI_TYPE,
990 	CPUCP_NUM_OF_MSI_TYPES
991 };
992 
993 /*
994  * PLL enumeration table used for all ASICs and future SW versions.
995  * For future ASIC-LKD compatibility, we can only add new enumerations.
996  * at the end of the table.
997  * Changing the order of entries or removing entries is not allowed.
998  */
999 enum pll_index {
1000 	CPU_PLL = 0,
1001 	PCI_PLL = 1,
1002 	NIC_PLL = 2,
1003 	DMA_PLL = 3,
1004 	MESH_PLL = 4,
1005 	MME_PLL = 5,
1006 	TPC_PLL = 6,
1007 	IF_PLL = 7,
1008 	SRAM_PLL = 8,
1009 	NS_PLL = 9,
1010 	HBM_PLL = 10,
1011 	MSS_PLL = 11,
1012 	DDR_PLL = 12,
1013 	VID_PLL = 13,
1014 	BANK_PLL = 14,
1015 	MMU_PLL = 15,
1016 	IC_PLL = 16,
1017 	MC_PLL = 17,
1018 	EMMC_PLL = 18,
1019 	D2D_PLL = 19,
1020 	CS_PLL = 20,
1021 	C2C_PLL = 21,
1022 	NCH_PLL = 22,
1023 	C2M_PLL = 23,
1024 	PLL_MAX
1025 };
1026 
1027 enum rl_index {
1028 	TPC_RL = 0,
1029 	MME_RL,
1030 	EDMA_RL,
1031 };
1032 
1033 enum pvt_index {
1034 	PVT_SW,
1035 	PVT_SE,
1036 	PVT_NW,
1037 	PVT_NE
1038 };
1039 
1040 /* Event Queue Packets */
1041 
1042 struct eq_generic_event {
1043 	__le64 data[7];
1044 };
1045 
1046 /*
1047  * CpuCP info
1048  */
1049 
1050 #define CARD_NAME_MAX_LEN		16
1051 #define CPUCP_MAX_SENSORS		128
1052 #define CPUCP_MAX_NICS			128
1053 #define CPUCP_LANES_PER_NIC		4
1054 #define CPUCP_NIC_QSFP_EEPROM_MAX_LEN	1024
1055 #define CPUCP_MAX_NIC_LANES		(CPUCP_MAX_NICS * CPUCP_LANES_PER_NIC)
1056 #define CPUCP_NIC_MASK_ARR_LEN		((CPUCP_MAX_NICS + 63) / 64)
1057 #define CPUCP_NIC_POLARITY_ARR_LEN	((CPUCP_MAX_NIC_LANES + 63) / 64)
1058 #define CPUCP_HBM_ROW_REPLACE_MAX	32
1059 
1060 struct cpucp_sensor {
1061 	__le32 type;
1062 	__le32 flags;
1063 };
1064 
1065 /**
1066  * struct cpucp_card_types - ASIC card type.
1067  * @cpucp_card_type_pci: PCI card.
1068  * @cpucp_card_type_pmc: PCI Mezzanine Card.
1069  */
1070 enum cpucp_card_types {
1071 	cpucp_card_type_pci,
1072 	cpucp_card_type_pmc
1073 };
1074 
1075 #define CPUCP_SEC_CONF_ENABLED_SHIFT	0
1076 #define CPUCP_SEC_CONF_ENABLED_MASK	0x00000001
1077 
1078 #define CPUCP_SEC_CONF_FLASH_WP_SHIFT	1
1079 #define CPUCP_SEC_CONF_FLASH_WP_MASK	0x00000002
1080 
1081 #define CPUCP_SEC_CONF_EEPROM_WP_SHIFT	2
1082 #define CPUCP_SEC_CONF_EEPROM_WP_MASK	0x00000004
1083 
1084 /**
1085  * struct cpucp_security_info - Security information.
1086  * @config: configuration bit field
1087  * @keys_num: number of stored keys
1088  * @revoked_keys: revoked keys bit field
1089  * @min_svn: minimal security version
1090  */
1091 struct cpucp_security_info {
1092 	__u8 config;
1093 	__u8 keys_num;
1094 	__u8 revoked_keys;
1095 	__u8 min_svn;
1096 };
1097 
1098 /**
1099  * struct cpucp_info - Info from CpuCP that is necessary to the host's driver
1100  * @sensors: available sensors description.
1101  * @kernel_version: CpuCP linux kernel version.
1102  * @reserved: reserved field.
1103  * @card_type: card configuration type.
1104  * @card_location: in a server, each card has different connections topology
1105  *                 depending on its location (relevant for PMC card type)
1106  * @cpld_version: CPLD programmed F/W version.
1107  * @infineon_version: Infineon main DC-DC version.
1108  * @fuse_version: silicon production FUSE information.
1109  * @thermal_version: thermald S/W version.
1110  * @cpucp_version: CpuCP S/W version.
1111  * @infineon_second_stage_version: Infineon 2nd stage DC-DC version.
1112  * @dram_size: available DRAM size.
1113  * @card_name: card name that will be displayed in HWMON subsystem on the host
1114  * @tpc_binning_mask: TPC binning mask, 1 bit per TPC instance
1115  *                    (0 = functional, 1 = binned)
1116  * @decoder_binning_mask: Decoder binning mask, 1 bit per decoder instance
1117  *                        (0 = functional, 1 = binned), maximum 1 per dcore
1118  * @sram_binning: Categorize SRAM functionality
1119  *                (0 = fully functional, 1 = lower-half is not functional,
1120  *                 2 = upper-half is not functional)
1121  * @sec_info: security information
1122  * @pll_map: Bit map of supported PLLs for current ASIC version.
1123  * @mme_binning_mask: MME binning mask,
1124  *                    bits [0:6]   <==> dcore0 mme fma
1125  *                    bits [7:13]  <==> dcore1 mme fma
1126  *                    bits [14:20] <==> dcore0 mme ima
1127  *                    bits [21:27] <==> dcore1 mme ima
1128  *                    For each group, if the 6th bit is set then first 5 bits
1129  *                    represent the col's idx [0-31], otherwise these bits are
1130  *                    ignored, and col idx 32 is binned. 7th bit is don't care.
1131  * @dram_binning_mask: DRAM binning mask, 1 bit per dram instance
1132  *                     (0 = functional 1 = binned)
1133  * @memory_repair_flag: eFuse flag indicating memory repair
1134  * @edma_binning_mask: EDMA binning mask, 1 bit per EDMA instance
1135  *                     (0 = functional 1 = binned)
1136  * @xbar_binning_mask: Xbar binning mask, 1 bit per Xbar instance
1137  *                     (0 = functional 1 = binned)
1138  * @interposer_version: Interposer version programmed in eFuse
1139  * @substrate_version: Substrate version programmed in eFuse
1140  * @fw_hbm_region_size: Size in bytes of FW reserved region in HBM.
1141  * @fw_os_version: Firmware OS Version
1142  */
1143 struct cpucp_info {
1144 	struct cpucp_sensor sensors[CPUCP_MAX_SENSORS];
1145 	__u8 kernel_version[VERSION_MAX_LEN];
1146 	__le32 reserved;
1147 	__le32 card_type;
1148 	__le32 card_location;
1149 	__le32 cpld_version;
1150 	__le32 infineon_version;
1151 	__u8 fuse_version[VERSION_MAX_LEN];
1152 	__u8 thermal_version[VERSION_MAX_LEN];
1153 	__u8 cpucp_version[VERSION_MAX_LEN];
1154 	__le32 infineon_second_stage_version;
1155 	__le64 dram_size;
1156 	char card_name[CARD_NAME_MAX_LEN];
1157 	__le64 tpc_binning_mask;
1158 	__le64 decoder_binning_mask;
1159 	__u8 sram_binning;
1160 	__u8 dram_binning_mask;
1161 	__u8 memory_repair_flag;
1162 	__u8 edma_binning_mask;
1163 	__u8 xbar_binning_mask;
1164 	__u8 interposer_version;
1165 	__u8 substrate_version;
1166 	__u8 reserved2;
1167 	struct cpucp_security_info sec_info;
1168 	__le32 fw_hbm_region_size;
1169 	__u8 pll_map[PLL_MAP_LEN];
1170 	__le64 mme_binning_mask;
1171 	__u8 fw_os_version[VERSION_MAX_LEN];
1172 };
1173 
1174 struct cpucp_mac_addr {
1175 	__u8 mac_addr[ETH_ALEN];
1176 };
1177 
1178 enum cpucp_serdes_type {
1179 	TYPE_1_SERDES_TYPE,
1180 	TYPE_2_SERDES_TYPE,
1181 	HLS1_SERDES_TYPE,
1182 	HLS1H_SERDES_TYPE,
1183 	HLS2_SERDES_TYPE,
1184 	HLS2_TYPE_1_SERDES_TYPE,
1185 	MAX_NUM_SERDES_TYPE,		/* number of types */
1186 	UNKNOWN_SERDES_TYPE = 0xFFFF	/* serdes_type is u16 */
1187 };
1188 
1189 struct cpucp_nic_info {
1190 	struct cpucp_mac_addr mac_addrs[CPUCP_MAX_NICS];
1191 	__le64 link_mask[CPUCP_NIC_MASK_ARR_LEN];
1192 	__le64 pol_tx_mask[CPUCP_NIC_POLARITY_ARR_LEN];
1193 	__le64 pol_rx_mask[CPUCP_NIC_POLARITY_ARR_LEN];
1194 	__le64 link_ext_mask[CPUCP_NIC_MASK_ARR_LEN];
1195 	__u8 qsfp_eeprom[CPUCP_NIC_QSFP_EEPROM_MAX_LEN];
1196 	__le64 auto_neg_mask[CPUCP_NIC_MASK_ARR_LEN];
1197 	__le16 serdes_type; /* enum cpucp_serdes_type */
1198 	__le16 tx_swap_map[CPUCP_MAX_NICS];
1199 	__u8 reserved[6];
1200 };
1201 
1202 #define PAGE_DISCARD_MAX	64
1203 
1204 struct page_discard_info {
1205 	__u8 num_entries;
1206 	__u8 reserved[7];
1207 	__le32 mmu_page_idx[PAGE_DISCARD_MAX];
1208 };
1209 
1210 /*
1211  * struct frac_val - fracture value represented by "integer.frac".
1212  * @integer: the integer part of the fracture value;
1213  * @frac: the fracture part of the fracture value.
1214  */
1215 struct frac_val {
1216 	union {
1217 		struct {
1218 			__le16 integer;
1219 			__le16 frac;
1220 		};
1221 		__le32 val;
1222 	};
1223 };
1224 
1225 /*
1226  * struct ser_val - the SER (symbol error rate) value is represented by "integer * 10 ^ -exp".
1227  * @integer: the integer part of the SER value;
1228  * @exp: the exponent part of the SER value.
1229  */
1230 struct ser_val {
1231 	__le16 integer;
1232 	__le16 exp;
1233 };
1234 
1235 /*
1236  * struct cpucp_nic_status - describes the status of a NIC port.
1237  * @port: NIC port index.
1238  * @bad_format_cnt: e.g. CRC.
1239  * @responder_out_of_sequence_psn_cnt: e.g NAK.
1240  * @high_ber_reinit_cnt: link reinit due to high BER.
1241  * @correctable_err_cnt: e.g. bit-flip.
1242  * @uncorrectable_err_cnt: e.g. MAC errors.
1243  * @retraining_cnt: re-training counter.
1244  * @up: is port up.
1245  * @pcs_link: has PCS link.
1246  * @phy_ready: is PHY ready.
1247  * @auto_neg: is Autoneg enabled.
1248  * @timeout_retransmission_cnt: timeout retransmission events.
1249  * @high_ber_cnt: high ber events.
1250  * @pre_fec_ser: pre FEC SER value.
1251  * @post_fec_ser: post FEC SER value.
1252  * @throughput: measured throughput.
1253  * @latency: measured latency.
1254  */
1255 struct cpucp_nic_status {
1256 	__le32 port;
1257 	__le32 bad_format_cnt;
1258 	__le32 responder_out_of_sequence_psn_cnt;
1259 	__le32 high_ber_reinit;
1260 	__le32 correctable_err_cnt;
1261 	__le32 uncorrectable_err_cnt;
1262 	__le32 retraining_cnt;
1263 	__u8 up;
1264 	__u8 pcs_link;
1265 	__u8 phy_ready;
1266 	__u8 auto_neg;
1267 	__le32 timeout_retransmission_cnt;
1268 	__le32 high_ber_cnt;
1269 	struct ser_val pre_fec_ser;
1270 	struct ser_val post_fec_ser;
1271 	struct frac_val bandwidth;
1272 	struct frac_val lat;
1273 };
1274 
1275 enum cpucp_hbm_row_replace_cause {
1276 	REPLACE_CAUSE_DOUBLE_ECC_ERR,
1277 	REPLACE_CAUSE_MULTI_SINGLE_ECC_ERR,
1278 };
1279 
1280 struct cpucp_hbm_row_info {
1281 	__u8 hbm_idx;
1282 	__u8 pc;
1283 	__u8 sid;
1284 	__u8 bank_idx;
1285 	__le16 row_addr;
1286 	__u8 replaced_row_cause; /* enum cpucp_hbm_row_replace_cause */
1287 	__u8 pad;
1288 };
1289 
1290 struct cpucp_hbm_row_replaced_rows_info {
1291 	__le16 num_replaced_rows;
1292 	__u8 pad[6];
1293 	struct cpucp_hbm_row_info replaced_rows[CPUCP_HBM_ROW_REPLACE_MAX];
1294 };
1295 
1296 enum cpu_reset_status {
1297 	CPU_RST_STATUS_NA = 0,
1298 	CPU_RST_STATUS_SOFT_RST_DONE = 1,
1299 };
1300 
1301 #define SEC_PCR_DATA_BUF_SZ	256
1302 #define SEC_PCR_QUOTE_BUF_SZ	510	/* (512 - 2) 2 bytes used for size */
1303 #define SEC_SIGNATURE_BUF_SZ	255	/* (256 - 1) 1 byte used for size */
1304 #define SEC_PUB_DATA_BUF_SZ	510	/* (512 - 2) 2 bytes used for size */
1305 #define SEC_CERTIFICATE_BUF_SZ	2046	/* (2048 - 2) 2 bytes used for size */
1306 
1307 /*
1308  * struct cpucp_sec_attest_info - attestation report of the boot
1309  * @pcr_data: raw values of the PCR registers
1310  * @pcr_num_reg: number of PCR registers in the pcr_data array
1311  * @pcr_reg_len: length of each PCR register in the pcr_data array (bytes)
1312  * @nonce: number only used once. random number provided by host. this also
1313  *	    passed to the quote command as a qualifying data.
1314  * @pcr_quote_len: length of the attestation quote data (bytes)
1315  * @pcr_quote: attestation report data structure
1316  * @quote_sig_len: length of the attestation report signature (bytes)
1317  * @quote_sig: signature structure of the attestation report
1318  * @pub_data_len: length of the public data (bytes)
1319  * @public_data: public key for the signed attestation
1320  *		 (outPublic + name + qualifiedName)
1321  * @certificate_len: length of the certificate (bytes)
1322  * @certificate: certificate for the attestation signing key
1323  */
1324 struct cpucp_sec_attest_info {
1325 	__u8 pcr_data[SEC_PCR_DATA_BUF_SZ];
1326 	__u8 pcr_num_reg;
1327 	__u8 pcr_reg_len;
1328 	__le16 pad0;
1329 	__le32 nonce;
1330 	__le16 pcr_quote_len;
1331 	__u8 pcr_quote[SEC_PCR_QUOTE_BUF_SZ];
1332 	__u8 quote_sig_len;
1333 	__u8 quote_sig[SEC_SIGNATURE_BUF_SZ];
1334 	__le16 pub_data_len;
1335 	__u8 public_data[SEC_PUB_DATA_BUF_SZ];
1336 	__le16 certificate_len;
1337 	__u8 certificate[SEC_CERTIFICATE_BUF_SZ];
1338 };
1339 
1340 /*
1341  * struct cpucp_dev_info_signed - device information signed by a secured device
1342  * @info: device information structure as defined above
1343  * @nonce: number only used once. random number provided by host. this number is
1344  *	   hashed and signed along with the device information.
1345  * @info_sig_len: length of the attestation signature (bytes)
1346  * @info_sig: signature of the info + nonce data.
1347  * @pub_data_len: length of the public data (bytes)
1348  * @public_data: public key info signed info data
1349  *		 (outPublic + name + qualifiedName)
1350  * @certificate_len: length of the certificate (bytes)
1351  * @certificate: certificate for the signing key
1352  */
1353 struct cpucp_dev_info_signed {
1354 	struct cpucp_info info;	/* assumed to be 64bit aligned */
1355 	__le32 nonce;
1356 	__le32 pad0;
1357 	__u8 info_sig_len;
1358 	__u8 info_sig[SEC_SIGNATURE_BUF_SZ];
1359 	__le16 pub_data_len;
1360 	__u8 public_data[SEC_PUB_DATA_BUF_SZ];
1361 	__le16 certificate_len;
1362 	__u8 certificate[SEC_CERTIFICATE_BUF_SZ];
1363 };
1364 
1365 #define DCORE_MON_REGS_SZ	512
1366 /*
1367  * struct dcore_monitor_regs_data - DCORE monitor regs data.
1368  * the structure follows sync manager block layout. Obsolete.
1369  * @mon_pay_addrl: array of payload address low bits.
1370  * @mon_pay_addrh: array of payload address high bits.
1371  * @mon_pay_data: array of payload data.
1372  * @mon_arm: array of monitor arm.
1373  * @mon_status: array of monitor status.
1374  */
1375 struct dcore_monitor_regs_data {
1376 	__le32 mon_pay_addrl[DCORE_MON_REGS_SZ];
1377 	__le32 mon_pay_addrh[DCORE_MON_REGS_SZ];
1378 	__le32 mon_pay_data[DCORE_MON_REGS_SZ];
1379 	__le32 mon_arm[DCORE_MON_REGS_SZ];
1380 	__le32 mon_status[DCORE_MON_REGS_SZ];
1381 };
1382 
1383 /* contains SM data for each SYNC_MNGR (Obsolete) */
1384 struct cpucp_monitor_dump {
1385 	struct dcore_monitor_regs_data sync_mngr_w_s;
1386 	struct dcore_monitor_regs_data sync_mngr_e_s;
1387 	struct dcore_monitor_regs_data sync_mngr_w_n;
1388 	struct dcore_monitor_regs_data sync_mngr_e_n;
1389 };
1390 
1391 /*
1392  * The Type of the generic request (and other input arguments) will be fetched from user by reading
1393  * from "pkt_subidx" field in struct cpucp_packet.
1394  *
1395  * HL_PASSTHROUGHT_VERSIONS	- Fetch all firmware versions.
1396  */
1397 enum hl_passthrough_type {
1398 	HL_PASSTHROUGH_VERSIONS,
1399 };
1400 
1401 #endif /* CPUCP_IF_H */
1402