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Searched refs:PACKET3_BASE_INDEX (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dsi_enums.h174 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
Dnvd.h57 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
Dsoc15d.h88 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
Dvid.h114 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
Dcikd.h232 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
Dsid.h1667 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
Dgfx_v6_0.c2004 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v6_0_cp_gfx_start()
Dgfx_v7_0.c2473 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v7_0_cp_gfx_start()
Dgfx_v8_0.c4195 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v8_0_cp_gfx_start()
Dgfx_v9_0.c3078 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v9_0_cp_gfx_start()
Dgfx_v10_0.c6002 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v10_0_cp_gfx_start()
/drivers/gpu/drm/radeon/
Dsid.h1604 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
Dcikd.h1700 #define PACKET3_BASE_INDEX(x) ((x) << 0) macro
Dsi.c3577 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in si_cp_start()
Dcik.c3991 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in cik_cp_gfx_start()