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Searched refs:PCI_DEV_REG1 (Results 1 – 4 of 4) sorted by relevance

/drivers/net/ethernet/marvell/
Dsky2.c699 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); in sky2_phy_power_up()
705 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); in sky2_phy_power_up()
707 sky2_pci_read32(hw, PCI_DEV_REG1); in sky2_phy_power_up()
764 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); in sky2_phy_power_down()
766 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); in sky2_phy_power_down()
867 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); in sky2_wol_init()
869 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); in sky2_wol_init()
Dsky2.h12 PCI_DEV_REG1 = 0x40, enumerator
Dskge.h10 #define PCI_DEV_REG1 0x40 macro
Dskge.c3629 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg); in skge_reset()
3631 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); in skge_reset()