| /drivers/net/ethernet/intel/igc/ |
| D | igc_phy.c | 75 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igc_phy_has_link()
86 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igc_phy_has_link()
407 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igc_wait_autoneg()
410 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igc_wait_autoneg()
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| D | igc_mac.c | 481 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, in igc_config_fc_after_link_up()
485 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, in igc_config_fc_after_link_up()
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| D | igc_defines.h | 623 #define PHY_STATUS 0x01 /* Status Register */ macro
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| /drivers/net/ethernet/intel/e1000/ |
| D | e1000_hw.c | 1466 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); in e1000_setup_copper_link()
1469 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); in e1000_setup_copper_link()
1779 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); in e1000_phy_force_speed_duplex()
1784 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); in e1000_phy_force_speed_duplex()
1813 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); in e1000_phy_force_speed_duplex()
1818 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); in e1000_phy_force_speed_duplex()
2084 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); in e1000_config_fc_after_link_up()
2087 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); in e1000_config_fc_after_link_up()
2407 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); in e1000_check_for_link()
2410 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); in e1000_check_for_link()
[all …]
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| D | e1000_hw.h | 2479 #define PHY_STATUS 0x01 /* Status Register */ macro
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| /drivers/gpu/drm/hisilicon/kirin/ |
| D | dw_dsi_reg.h | 62 #define PHY_STATUS 0xB0 /* D-PHY PPI status interface */ macro
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| D | dw_drm_dsi.c | 436 val = readl(base + PHY_STATUS); in dsi_set_mipi_phy()
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| /drivers/pci/controller/dwc/ |
| D | pcie-artpec6.c | 75 #define PHY_STATUS 0x118 macro
162 val = readl(artpec6_pcie->phy_base + PHY_STATUS); in artpec6_pcie_wait_for_phy_a6()
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| /drivers/phy/freescale/ |
| D | phy-fsl-imx8qm-lvds-phy.c | 42 #define PHY_STATUS 0x10 macro
129 ret = regmap_read_poll_timeout(priv->regmap, PHY_STATUS, locked, in mixel_lvds_phy_power_on()
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| /drivers/net/ethernet/oki-semi/pch_gbe/ |
| D | pch_gbe_phy.c | 17 #define PHY_STATUS 0x01 /* Status Regiser */ macro
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| /drivers/net/ethernet/intel/igb/ |
| D | e1000_phy.c | 1596 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igb_wait_autoneg()
1599 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igb_wait_autoneg()
1633 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igb_phy_has_link()
1644 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igb_phy_has_link()
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| D | e1000_mac.c | 935 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, in igb_config_fc_after_link_up()
939 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, in igb_config_fc_after_link_up()
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| D | e1000_defines.h | 695 #define PHY_STATUS 0x01 /* Status Register */ macro
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| /drivers/gpu/drm/sprd/ |
| D | sprd_dsi.c | 91 #define PHY_STATUS 0x9C macro
228 if (dsi_reg_rd(ctx, PHY_STATUS, PHY_LOCK, 1)) in dphy_wait_pll_locked()
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