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Searched refs:PINMUX_IPSR_MSEL (Results 1 – 19 of 19) sorted by relevance

/drivers/pinctrl/renesas/
Dpfc-sh7734.c592 PINMUX_IPSR_MSEL(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0),
593 PINMUX_IPSR_MSEL(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1),
597 PINMUX_IPSR_MSEL(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0),
598 PINMUX_IPSR_MSEL(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1),
602 PINMUX_IPSR_MSEL(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0),
603 PINMUX_IPSR_MSEL(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1),
607 PINMUX_IPSR_MSEL(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0),
608 PINMUX_IPSR_MSEL(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1),
612 PINMUX_IPSR_MSEL(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0),
613 PINMUX_IPSR_MSEL(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1),
[all …]
Dpfc-r8a7790.c808 PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
809 PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
810 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
811 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
813 PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
814 PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
815 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
816 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
818 PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
819 PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
[all …]
Dpfc-r8a7791.c856 PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
857 PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
858 PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2),
861 PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
863 PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
865 PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
867 PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
869 PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
871 PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
875 PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
[all …]
Dpfc-r8a7794.c751 PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
754 PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
772 PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
773 PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
774 PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
776 PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
777 PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
778 PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
780 PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
783 PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
[all …]
Dpfc-r8a77470.c554 PINMUX_IPSR_MSEL(IP0_3_0, SSI_SCK1_C, SEL_SSI1_2),
555 PINMUX_IPSR_MSEL(IP0_3_0, RX3_C, SEL_SCIF3_2),
557 PINMUX_IPSR_MSEL(IP0_7_4, SSI_WS1_C, SEL_SSI1_2),
558 PINMUX_IPSR_MSEL(IP0_7_4, TX3_C, SEL_SCIF3_2),
560 PINMUX_IPSR_MSEL(IP0_11_8, SSI_SDATA1_C, SEL_SSI1_2),
561 PINMUX_IPSR_MSEL(IP0_11_8, RX4_E, SEL_SCIF4_4),
563 PINMUX_IPSR_MSEL(IP0_15_12, SSI_SCK0129_B, SEL_SSI0_1),
564 PINMUX_IPSR_MSEL(IP0_15_12, TX4_E, SEL_SCIF4_4),
566 PINMUX_IPSR_MSEL(IP0_19_16, SSI_WS0129_B, SEL_SSI0_1),
567 PINMUX_IPSR_MSEL(IP0_19_16, RX5_E, SEL_SCIF5_4),
[all …]
Dpfc-r8a7796.c654 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
657 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
658 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
661 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
662 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
665 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
666 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
681 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
682 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
683 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
[all …]
Dpfc-r8a77965.c654 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
657 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
658 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
661 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
662 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
665 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
666 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
682 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
683 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
684 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
[all …]
Dpfc-r8a77951.c648 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
651 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
652 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
655 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
656 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
659 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
660 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
665 PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0),
676 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
677 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
[all …]
Dpfc-r8a7779.c666 PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0),
668 PINMUX_IPSR_MSEL(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
669 PINMUX_IPSR_MSEL(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
670 PINMUX_IPSR_MSEL(IP0_2_0, TCLK0_C, SEL_TMU0_2),
677 PINMUX_IPSR_MSEL(IP0_5_3, HCTS1, SEL_HSCIF1_0),
687 PINMUX_IPSR_MSEL(IP0_11_10, SCK5_D, SEL_SCIF5_3),
688 PINMUX_IPSR_MSEL(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
690 PINMUX_IPSR_MSEL(IP0_13_12, RX5_D, SEL_SCIF5_3),
691 PINMUX_IPSR_MSEL(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
695 PINMUX_IPSR_MSEL(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
[all …]
Dpfc-r8a77990.c556 PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0),
559 PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0),
562 PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0),
568 PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0),
571 PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0),
572 PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1),
573 PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0),
576 PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
578 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0),
581 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
[all …]
Dpfc-r8a7778.c547 PINMUX_IPSR_MSEL(IP0_4_2, GPSCLK_C, SEL_GPS_C),
550 PINMUX_IPSR_MSEL(IP0_4_2, SDA2_B, SEL_I2C2_B),
554 PINMUX_IPSR_MSEL(IP0_7_5, GPSIN_C, SEL_GPS_C),
556 PINMUX_IPSR_MSEL(IP0_7_5, RX2_E, SEL_SCIF2_E),
557 PINMUX_IPSR_MSEL(IP0_7_5, SCL2_B, SEL_I2C2_B),
559 PINMUX_IPSR_MSEL(IP0_11_8, SD1_DAT2_A, SEL_SD1_A),
566 PINMUX_IPSR_MSEL(IP0_14_12, SD1_DAT3_A, SEL_SD1_A),
570 PINMUX_IPSR_MSEL(IP0_14_12, REMOCON_B, SEL_REMOCON_B),
591 PINMUX_IPSR_MSEL(IP1_0, HSPI_CS1_B, SEL_HSPI1_B),
594 PINMUX_IPSR_MSEL(IP1_1, HSPI_CLK1_B, SEL_HSPI1_B),
[all …]
Dpfc-r8a77995.c535 PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
536 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
541 PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0),
544 PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0),
547 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0),
548 PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0),
552 PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0),
553 PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1),
557 PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0),
558 PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1),
[all …]
Dpfc-r8a779f0.c427 PINMUX_IPSR_MSEL(IP0SR1_3_0, GP1_00, SEL_I2C0_0),
428 PINMUX_IPSR_MSEL(IP0SR1_3_0, TCLK1, SEL_I2C0_0),
429 PINMUX_IPSR_MSEL(IP0SR1_3_0, HSCK2, SEL_I2C0_0),
433 PINMUX_IPSR_MSEL(IP0SR1_7_4, GP1_01, SEL_I2C0_0),
434 PINMUX_IPSR_MSEL(IP0SR1_7_4, TCLK4, SEL_I2C0_0),
435 PINMUX_IPSR_MSEL(IP0SR1_7_4, HRX2, SEL_I2C0_0),
439 PINMUX_IPSR_MSEL(IP0SR1_11_8, GP1_02, SEL_I2C1_0),
440 PINMUX_IPSR_MSEL(IP0SR1_11_8, HTX2, SEL_I2C1_0),
441 PINMUX_IPSR_MSEL(IP0SR1_11_8, MSIOF2_SS1, SEL_I2C1_0),
442 PINMUX_IPSR_MSEL(IP0SR1_11_8, TSN2_MDC_A, SEL_I2C1_0),
[all …]
Dpfc-r8a77970.c429 PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0),
433 PINMUX_IPSR_MSEL(IP1_7_4, FSO_CFE_1_N_A, SEL_RFSO_0),
437 PINMUX_IPSR_MSEL(IP1_11_8, FSO_TOE_N_A, SEL_RFSO_0),
468 PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
514 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
518 PINMUX_IPSR_MSEL(IP3_23_20, SDA3_A, SEL_I2C3_0),
522 PINMUX_IPSR_MSEL(IP3_27_24, SCL3_A, SEL_I2C3_0),
526 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
531 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
543 PINMUX_IPSR_MSEL(IP4_15_12, PWM0_A, SEL_PWM0_0),
[all …]
Dpfc-r8a77980.c507 PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1),
511 PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
512 PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1),
516 PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
520 PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0),
525 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0),
530 PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0),
535 PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0),
536 PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0),
550 PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1),
[all …]
Dpfc-r8a779a0.c944 PINMUX_IPSR_MSEL(IP0SR2_11_8, GP2_02, SEL_I2C0_0),
945 PINMUX_IPSR_MSEL(IP0SR2_11_8, D3, SEL_I2C0_0),
949 PINMUX_IPSR_MSEL(IP0SR2_15_12, GP2_03, SEL_I2C0_0),
950 PINMUX_IPSR_MSEL(IP0SR2_15_12, D4, SEL_I2C0_0),
954 PINMUX_IPSR_MSEL(IP0SR2_19_16, GP2_04, SEL_I2C1_0),
955 PINMUX_IPSR_MSEL(IP0SR2_19_16, MSIOF4_RXD, SEL_I2C1_0),
956 PINMUX_IPSR_MSEL(IP0SR2_19_16, D5, SEL_I2C1_0),
960 PINMUX_IPSR_MSEL(IP0SR2_23_20, GP2_05, SEL_I2C1_0),
961 PINMUX_IPSR_MSEL(IP0SR2_23_20, HSCK2, SEL_I2C1_0),
962 PINMUX_IPSR_MSEL(IP0SR2_23_20, MSIOF4_TXD, SEL_I2C1_0),
[all …]
Dpfc-r8a779g0.c1193 PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_0),
1194 PINMUX_IPSR_MSEL(IP0SR8_7_4, SDA0, SEL_SDA0_0),
1195 PINMUX_IPSR_MSEL(IP0SR8_11_8, SCL1, SEL_SCL1_0),
1196 PINMUX_IPSR_MSEL(IP0SR8_15_12, SDA1, SEL_SDA1_0),
1197 PINMUX_IPSR_MSEL(IP0SR8_19_16, SCL2, SEL_SCL2_0),
1198 PINMUX_IPSR_MSEL(IP0SR8_23_20, SDA2, SEL_SDA2_0),
1199 PINMUX_IPSR_MSEL(IP0SR8_27_24, SCL3, SEL_SCL3_0),
1200 PINMUX_IPSR_MSEL(IP0SR8_31_28, SDA3, SEL_SDA3_0),
1203 PINMUX_IPSR_MSEL(IP1SR8_3_0, SCL4, SEL_SCL4_0),
1204 PINMUX_IPSR_MSEL(IP1SR8_3_0, HRX2, SEL_SCL4_0),
[all …]
Dpfc-r8a7792.c624 PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
627 PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
630 PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
633 PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
657 PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
659 PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
661 PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
663 PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
Dsh_pfc.h404 #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \ macro