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Searched refs:PLL_CNTL__PLL_POST_DIV_SRC__SHIFT (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_sh_mask.h8330 #define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x00000003 macro
Ddce_8_0_sh_mask.h2094 #define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3 macro
Ddce_11_0_sh_mask.h11462 #define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3 macro
Ddce_10_0_sh_mask.h11650 #define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3 macro