Home
last modified time | relevance | path

Searched refs:PLL_ODIV0_REG (Results 1 – 1 of 1) sorted by relevance

/drivers/clk/axs10x/
Di2s_pll_clock.c21 #define PLL_ODIV0_REG 0x8 macro
106 odiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_ODIV0_REG)); in i2s_pll_recalc_rate()
146 i2s_pll_write(clk, PLL_ODIV0_REG, pll_cfg[i].odiv0); in i2s_pll_set_rate()