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Searched refs:PLL_P2_DIVIDE_BY_4 (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/gma500/
Dpsb_intel_display.c362 if (dpll & PLL_P2_DIVIDE_BY_4) in psb_intel_crtc_clock_get()
Dpsb_intel_reg.h255 #define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required macro
Dcdv_intel_display.c897 if (dpll & PLL_P2_DIVIDE_BY_4) in cdv_intel_crtc_clock_get()
/drivers/gpu/drm/i915/display/
Dintel_dpll.c905 dpll |= PLL_P2_DIVIDE_BY_4; in i8xx_compute_dpll()
Dintel_display.c3910 if (dpll & PLL_P2_DIVIDE_BY_4) in i9xx_crtc_clock_get()
7918 PLL_P2_DIVIDE_BY_4 | in i830_enable_pipe()
/drivers/gpu/drm/i915/
Di915_reg.h1481 #define PLL_P2_DIVIDE_BY_4 (1 << 23) macro